| Message ID | 20190719210326.15466-8-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement ARMv8.1-VHE | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/cpu.h | 7 ------- > target/arm/helper.c | 6 +++++- > 2 files changed, 5 insertions(+), 8 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index e6a76d14c6..e37008a4f7 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1366,13 +1366,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) > #define HCR_ATA (1ULL << 56) > #define HCR_DCT (1ULL << 57) > > -/* > - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to > - * HCR_MASK and then clear it again if the feature bit is not set in > - * hcr_write(). > - */ > -#define HCR_MASK ((1ULL << 34) - 1) > - > #define SCR_NS (1U << 0) > #define SCR_IRQ (1U << 1) > #define SCR_FIQ (1U << 2) > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 3a9f35bf4b..0a55096770 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -4623,7 +4623,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { > static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > { > ARMCPU *cpu = env_archcpu(env); > - uint64_t valid_mask = HCR_MASK; > + /* Begin with bits defined in base ARMv8.0. */ > + uint64_t valid_mask = MAKE_64BIT_MASK(0, 34); > > if (arm_feature(env, ARM_FEATURE_EL3)) { > valid_mask &= ~HCR_HCD; > @@ -4637,6 +4638,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > */ > valid_mask &= ~HCR_TSC; > } > + if (cpu_isar_feature(aa64_vh, cpu)) { > + valid_mask |= HCR_E2H; > + } > if (cpu_isar_feature(aa64_lor, cpu)) { > valid_mask |= HCR_TLOR; > } -- Alex Bennée
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e6a76d14c6..e37008a4f7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1366,13 +1366,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_ATA (1ULL << 56) #define HCR_DCT (1ULL << 57) -/* - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to - * HCR_MASK and then clear it again if the feature bit is not set in - * hcr_write(). - */ -#define HCR_MASK ((1ULL << 34) - 1) - #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3a9f35bf4b..0a55096770 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4623,7 +4623,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); - uint64_t valid_mask = HCR_MASK; + /* Begin with bits defined in base ARMv8.0. */ + uint64_t valid_mask = MAKE_64BIT_MASK(0, 34); if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &= ~HCR_HCD; @@ -4637,6 +4638,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) */ valid_mask &= ~HCR_TSC; } + if (cpu_isar_feature(aa64_vh, cpu)) { + valid_mask |= HCR_E2H; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |= HCR_TLOR; }
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 7 ------- target/arm/helper.c | 6 +++++- 2 files changed, 5 insertions(+), 8 deletions(-) -- 2.17.1