| Message ID | 20190719210326.15466-19-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement ARMv8.1-VHE | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Use this function in many more places in order to select > the correct control. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/cpu.h | 10 ++++++---- > target/arm/arch_dump.c | 2 +- > target/arm/helper-a64.c | 2 +- > target/arm/helper.c | 10 +++++----- > target/arm/pauth_helper.c | 9 +-------- > 5 files changed, 14 insertions(+), 19 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 7310adfd9b..7efbb488d9 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3104,11 +3104,13 @@ static inline bool arm_sctlr_b(CPUARMState *env) > static inline uint64_t arm_sctlr(CPUARMState *env, int el) > { > if (el == 0) { > - /* FIXME: ARMv8.1-VHE S2 translation regime. */ > - return env->cp15.sctlr_el[1]; > - } else { > - return env->cp15.sctlr_el[el]; > + if (arm_el_is_aa64(env, 2) && (arm_hcr_el2_eff(env) & HCR_E2H)) { > + el = 2; > + } else { > + el = 1; > + } > } > + return env->cp15.sctlr_el[el]; > } > > > diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c > index 26a2c09868..5fbd008d8c 100644 > --- a/target/arm/arch_dump.c > +++ b/target/arm/arch_dump.c > @@ -320,7 +320,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, > * dump a hypervisor that happens to be running an opposite-endian > * kernel. > */ > - info->d_endian = (env->cp15.sctlr_el[1] & SCTLR_EE) != 0 > + info->d_endian = (arm_sctlr(env, 1) & SCTLR_EE) != 0 > ? ELFDATA2MSB : ELFDATA2LSB; > > return 0; > diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c > index 060699b901..3bf1b731e7 100644 > --- a/target/arm/helper-a64.c > +++ b/target/arm/helper-a64.c > @@ -70,7 +70,7 @@ static void daif_check(CPUARMState *env, uint32_t op, > uint32_t imm, uintptr_t ra) > { > /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ > - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { > + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { > raise_exception_ra(env, EXCP_UDEF, > syn_aa64_sysregtrap(0, extract32(op, 0, 3), > extract32(op, 3, 3), 4, > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 54c328b844..db13a8f9c0 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3868,7 +3868,7 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, > static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, > bool isread) > { > - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { > + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -3887,7 +3887,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, > /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless > * SCTLR_EL1.UCI is set. > */ > - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { > + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -4114,7 +4114,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, > /* We don't implement EL2, so the only control on DC ZVA is the > * bit in the SCTLR which can prohibit access for EL0. > */ > - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { > + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_DZE)) { > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -5344,7 +5344,7 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, > /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, > * but the AArch32 CTR has its own reginfo struct) > */ > - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { > + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCT)) { > return CP_ACCESS_TRAP; > } > return CP_ACCESS_OK; > @@ -8161,7 +8161,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, > env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; > /* Set new mode endianness */ > env->uncached_cpsr &= ~CPSR_E; > - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { > + if (arm_sctlr(env, arm_current_el(env)) & SCTLR_EE) { > env->uncached_cpsr |= CPSR_E; > } > /* J and IL must always be cleared for exception entry */ > diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c > index d3194f2043..42c9141bb7 100644 > --- a/target/arm/pauth_helper.c > +++ b/target/arm/pauth_helper.c > @@ -386,14 +386,7 @@ static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra) > > static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) > { > - uint32_t sctlr; > - if (el == 0) { > - /* FIXME: ARMv8.1-VHE S2 translation regime. */ > - sctlr = env->cp15.sctlr_el[1]; > - } else { > - sctlr = env->cp15.sctlr_el[el]; > - } > - return (sctlr & bit) != 0; > + return (arm_sctlr(env, el) & bit) != 0; > } > > uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y) -- Alex Bennée
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7310adfd9b..7efbb488d9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3104,11 +3104,13 @@ static inline bool arm_sctlr_b(CPUARMState *env) static inline uint64_t arm_sctlr(CPUARMState *env, int el) { if (el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - return env->cp15.sctlr_el[1]; - } else { - return env->cp15.sctlr_el[el]; + if (arm_el_is_aa64(env, 2) && (arm_hcr_el2_eff(env) & HCR_E2H)) { + el = 2; + } else { + el = 1; + } } + return env->cp15.sctlr_el[el]; } diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 26a2c09868..5fbd008d8c 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -320,7 +320,7 @@ int cpu_get_dump_info(ArchDumpInfo *info, * dump a hypervisor that happens to be running an opposite-endian * kernel. */ - info->d_endian = (env->cp15.sctlr_el[1] & SCTLR_EE) != 0 + info->d_endian = (arm_sctlr(env, 1) & SCTLR_EE) != 0 ? ELFDATA2MSB : ELFDATA2LSB; return 0; diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 060699b901..3bf1b731e7 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -70,7 +70,7 @@ static void daif_check(CPUARMState *env, uint32_t op, uint32_t imm, uintptr_t ra) { /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { raise_exception_ra(env, EXCP_UDEF, syn_aa64_sysregtrap(0, extract32(op, 0, 3), extract32(op, 3, 3), 4, diff --git a/target/arm/helper.c b/target/arm/helper.c index 54c328b844..db13a8f9c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3868,7 +3868,7 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -3887,7 +3887,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless * SCTLR_EL1.UCI is set. */ - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -4114,7 +4114,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, /* We don't implement EL2, so the only control on DC ZVA is the * bit in the SCTLR which can prohibit access for EL0. */ - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_DZE)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -5344,7 +5344,7 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, * but the AArch32 CTR has its own reginfo struct) */ - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { + if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCT)) { return CP_ACCESS_TRAP; } return CP_ACCESS_OK; @@ -8161,7 +8161,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; /* Set new mode endianness */ env->uncached_cpsr &= ~CPSR_E; - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + if (arm_sctlr(env, arm_current_el(env)) & SCTLR_EE) { env->uncached_cpsr |= CPSR_E; } /* J and IL must always be cleared for exception entry */ diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index d3194f2043..42c9141bb7 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -386,14 +386,7 @@ static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra) static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit) { - uint32_t sctlr; - if (el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr = env->cp15.sctlr_el[1]; - } else { - sctlr = env->cp15.sctlr_el[el]; - } - return (sctlr & bit) != 0; + return (arm_sctlr(env, el) & bit) != 0; } uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y)
Use this function in many more places in order to select the correct control. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 10 ++++++---- target/arm/arch_dump.c | 2 +- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 10 +++++----- target/arm/pauth_helper.c | 9 +-------- 5 files changed, 14 insertions(+), 19 deletions(-) -- 2.17.1