| Message ID | 20190719210326.15466-10-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement ARMv8.1-VHE | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > At the same time, add writefn to TTBR0_EL2 and TCR_EL2. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/helper.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d1bf31ab74..da2e0627b2 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3449,6 +3449,15 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, > } > } > > +static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + raw_write(env, ri, value); I wonder if the bellow would be better merged with: target/arm: Install asids for E2&0 translation regime And the commit message amended to say something like: "later patches will potentially update the asid" > + if (arm_hcr_el2_eff(env) & HCR_E2H) { > + /* The ASID field is active. */ > + } > +} > + > static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > @@ -4844,10 +4853,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .resetvalue = 0 }, > { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, > - .access = PL2_RW, > - /* no .writefn needed as this can't cause an ASID change; > - * no .raw_writefn or .resetfn needed as we never use mask/base_mask > - */ > + .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, > + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */ > .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, > { .name = "VTCR", .state = ARM_CP_STATE_AA32, > .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, > @@ -4881,7 +4888,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, > { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, > - .access = PL2_RW, .resetvalue = 0, > + .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, > .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, > { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, > .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, > @@ -6807,6 +6814,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, > .access = PL2_RW, > .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, > + { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, > + .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, > + .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, > REGINFO_SENTINEL > }; > define_arm_cp_regs(cpu, vhe_reginfo); Otherwise: Reviewed-by: Alex Bennée <alex.bennee@linaro.org> -- Alex Bennée
diff --git a/target/arm/helper.c b/target/arm/helper.c index d1bf31ab74..da2e0627b2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3449,6 +3449,15 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); + if (arm_hcr_el2_eff(env) & HCR_E2H) { + /* The ASID field is active. */ + } +} + static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -4844,10 +4853,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .resetvalue = 0 }, { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, - .access = PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */ .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name = "VTCR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, @@ -4881,7 +4888,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, - .access = PL2_RW, .resetvalue = 0, + .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6807,6 +6814,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, + { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, + .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, + .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vhe_reginfo);
At the same time, add writefn to TTBR0_EL2 and TCR_EL2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) -- 2.17.1