From patchwork Sat Jun 29 13:00:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 168158 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp730149ilk; Sat, 29 Jun 2019 06:08:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqw7CEHYVl4zvrZKhmDFUi7LK1aMjnEmt9iuuwCNCyk/ZoOQt1NXk9sxiQyhX1ydjp4T1zM0 X-Received: by 2002:a17:906:b203:: with SMTP id p3mr13746399ejz.145.1561813713894; Sat, 29 Jun 2019 06:08:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561813713; cv=none; d=google.com; s=arc-20160816; b=e0UfzT5m7tkNflVMT0HyiNxFkEJ8m97RKo4kFPzVTp5wlx/u5uGi0guaTTWqSYKS7h F7hBjnUxMtc9HtjkUc6dplEEqFgy5LaXHI76G+YJChofhnO9QqiVR3ryTCTgMrGpNRfm VmVLg6EsqHrvz3pQrcBn8WBfcOm7W/o6/O0l6Ane268nILsyFWTPkJyztc7MaF3QMRga JhBDSwBV7mZYMdYhWH0MidrkaIuhDWTMVfF2XfV5kyv+85W9C7lib9kTeaKXRutMswA1 AzG196LrcK1lvx5DrgSuXgXRITzk1ZTLqP3P6brWQNjmt/JaaPQRIFtZHn8EljIFPAPt EWnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=emP6dWoUPqOedFjKNUj+V8rg9amcwEcg4Kk6M44arTs=; b=F6/cQ2wooh3ohtWJ54sYpTP9clGmDz8OJXfLflFoWk+6sp+1T/VxfiISeVyAWd8ZG2 60TpSyo2I+g2OAlqCTa3HpHUIzKXS9RoCQ++U2C3ArhagBSewf2OmKQocv4KYhjbHaax /5cTEAdNFd5HAVrncbW82PTT0C3oJOeT26xqpTCtlINFt6ykAakcziX7f+U42qUkyjFO nRzBa870gcfHeJVja04SrRxRKP5TP3ee4WwKxuDfMURwdDeZD2zQY+A2/EoyT7udoEwo ofGAgUVq9kKhAatO0hJM1lVuXLZWyaop/oSH2s/DY7BGR//r2Xcw2TZ56uAA/g3qjnpt 5CiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bpb6uRVb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z19si3642102ejm.26.2019.06.29.06.08.33 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 29 Jun 2019 06:08:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bpb6uRVb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhD5k-0003ks-U9 for patch@linaro.org; Sat, 29 Jun 2019 09:08:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41345) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hhCyE-0007ze-7j for qemu-devel@nongnu.org; Sat, 29 Jun 2019 09:00:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hhCy9-0003cr-6p for qemu-devel@nongnu.org; Sat, 29 Jun 2019 09:00:44 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:38003) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hhCy8-0003Rr-KD for qemu-devel@nongnu.org; Sat, 29 Jun 2019 09:00:40 -0400 Received: by mail-wm1-x341.google.com with SMTP id s15so11444878wmj.3 for ; Sat, 29 Jun 2019 06:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=emP6dWoUPqOedFjKNUj+V8rg9amcwEcg4Kk6M44arTs=; b=bpb6uRVbngu7JnL0cxiBRFzetqIf/ZajCN02bzgJUPuLSP20iSeQ5ybNsygMGzrmU4 0D/U78WoWiD+w+Q7fbn99n/hOWyEGD51pYNa5dHmTqhrkOdGj/kvE20B/odbT8nUvO/s BVxFS2/M4Hl+riV+zHy+Ev6tzOpgAVOlSOnx/z4DgrWkgDYW2TQ2eRzIsa8ONVMxhe7+ nUeUnSORv0ep2IQxwwgXlz3ux1iOXJl9m6y39INiCma0ufpjwMenXnFa80NS+g0tf+nQ h0c/uN3sxFyLjiPBSYXds92c50sK87gLoq161UX7hFNMQc8s+cLbiR8w3yOd5MVwNrRL ugAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=emP6dWoUPqOedFjKNUj+V8rg9amcwEcg4Kk6M44arTs=; b=kKB6o3fjkHpLlba1TAn/CU5l5BCicc+D0LFe0TVFcQJYCdmy8zKaucYBuML6n7BjQU JCAkh4RA9tluvPwi8j42rwV6NUfrFdNcOHGJrYKOLTjkyFyWqNYapmsq4B+2MI/DzAiF bQmBpzairGhOFPZ5LAgU7fKWO9/9aTd0Jbxh/pWRyZrIvqLG1YFnKkBSeSCVvOTItJMD KPhQNkdUmNVqAHjc2ko+hMWJy6inOFaVC/YWm8+VqdBoAS+MjtStOaVpuoeWWG6mrBMe FozA3ujFUGR6+NN3bCx6e0DE8Q5oj7lnibtBotOd8PxzenN9tG+1MCmjNnY2AxsOv66x nBZQ== X-Gm-Message-State: APjAAAXzXBYSkReMbBA+1RS1FGhVyMA1j+g7aRcb2AD4TTRUd8dvfdvT 7aic4qVy7YrG8NO193TcMzhfHkCenJpMxQ== X-Received: by 2002:a1c:720e:: with SMTP id n14mr10796331wmc.53.1561813229143; Sat, 29 Jun 2019 06:00:29 -0700 (PDT) Received: from localhost.localdomain (93-34-153-63.ip50.fastwebnet.it. [93.34.153.63]) by smtp.gmail.com with ESMTPSA id d10sm4937676wro.18.2019.06.29.06.00.28 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 29 Jun 2019 06:00:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 29 Jun 2019 15:00:11 +0200 Message-Id: <20190629130017.2973-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190629130017.2973-1-richard.henderson@linaro.org> References: <20190629130017.2973-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v6 10/16] tcg/ppc: Support vector shift by immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com, hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For Altivec, this is done via vector shift by vector, and loading the immediate into a register. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 58 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 368c250c6a..766706fd30 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -152,7 +152,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 1 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index e19400609c..7ddef950f7 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -517,6 +517,16 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define VCMPGTUH VX4(582) #define VCMPGTUW VX4(646) +#define VSLB VX4(260) +#define VSLH VX4(324) +#define VSLW VX4(388) +#define VSRB VX4(516) +#define VSRH VX4(580) +#define VSRW VX4(644) +#define VSRAB VX4(772) +#define VSRAH VX4(836) +#define VSRAW VX4(900) + #define VAND VX4(1028) #define VANDC VX4(1092) #define VNOR VX4(1284) @@ -2863,8 +2873,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return vece <= MO_32; case INDEX_op_cmp_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: + case INDEX_op_sari_vec: return vece <= MO_32 ? -1 : 0; default: return 0; @@ -2971,7 +2987,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 }, smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 }, umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 }, - smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 }; + smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 }, + shlv_op[4] = { VSLB, VSLH, VSLW, 0 }, + shrv_op[4] = { VSRB, VSRH, VSRW, 0 }, + sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 }; TCGType type = vecl + TCG_TYPE_V64; TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; @@ -3018,6 +3037,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_umax_vec: insn = umax_op[vece]; break; + case INDEX_op_shlv_vec: + insn = shlv_op[vece]; + break; + case INDEX_op_shrv_vec: + insn = shrv_op[vece]; + break; + case INDEX_op_sarv_vec: + insn = sarv_op[vece]; + break; case INDEX_op_and_vec: insn = VAND; break; @@ -3062,6 +3090,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); } +static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGArg imm, TCGOpcode opci) +{ + TCGv_vec t1 = tcg_temp_new_vec(type); + + /* Splat w/bytes for xxspltib. */ + tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1)); + vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(t1)); + tcg_temp_free_vec(t1); +} + static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGCond cond) { @@ -3113,14 +3153,25 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, { va_list va; TCGv_vec v0, v1, v2; + TCGArg a2; va_start(va, a0); v0 = temp_tcgv_vec(arg_temp(a0)); v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); - v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + a2 = va_arg(va, TCGArg); switch (opc) { + case INDEX_op_shli_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); + break; + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); + break; + case INDEX_op_sari_vec: + expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); + break; case INDEX_op_cmp_vec: + v2 = temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; default: @@ -3321,6 +3372,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: