@@ -194,11 +194,6 @@ typedef struct Nios2CPU {
uint32_t fast_tlb_miss_addr;
} Nios2CPU;
-static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
-{
- return NIOS2_CPU(container_of(env, Nios2CPU, env));
-}
-
#define ENV_OFFSET offsetof(Nios2CPU, env)
void nios2_tcg_init(void);
@@ -54,12 +54,9 @@ static void nios2_pic_cpu_handler(void *opaque, int irq, int level)
void nios2_check_interrupts(CPUNios2State *env)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
-
if (env->irq_pending) {
env->irq_pending = 0;
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
}
}
@@ -61,7 +61,7 @@ unsigned int mmu_translate(CPUNios2State *env,
Nios2MMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
int vpn = vaddr >> 12;
@@ -103,7 +103,7 @@ unsigned int mmu_translate(CPUNios2State *env,
static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
{
CPUState *cs = env_cpu(env);
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
int idx;
MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));
@@ -127,7 +127,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
{
CPUState *cs = env_cpu(env);
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));
@@ -244,7 +244,7 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
void mmu_init(CPUNios2State *env)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
Nios2MMU *mmu = &env->mmu;
MMU_LOG(qemu_log("mmu_init\n"));
@@ -255,7 +255,7 @@ void mmu_init(CPUNios2State *env)
void dump_mmu(CPUNios2State *env)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
int i;
qemu_printf("MMU: ways %d, entries %d, pid bits %d\n",