[PULL,25/27] tcg: Use CPUClass::tlb_fill in cputlb.c

Message ID	20190510151944.22981-26-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Fri, 10 May 2019 08:19:42 -0700 Message-Id: <20190510151944.22981-26-richard.henderson@linaro.org> In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org> References: <20190510151944.22981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 25/27] tcg: Use CPUClass::tlb_fill in cputlb.c Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg: Add CPUClass::tlb_fill \| expand [PULL,00/27] tcg: Add CPUClass::tlb_fill [PULL,01/27] tcg: Add CPUClass::tlb_fill [PULL,02/27] target/alpha: Convert to CPUClass::tlb_fill [PULL,03/27] target/arm: Convert to CPUClass::tlb_fill [PULL,04/27] target/cris: Convert to CPUClass::tlb_fill [PULL,05/27] target/hppa: Convert to CPUClass::tlb_fill [PULL,06/27] target/i386: Convert to CPUClass::tlb_fill [PULL,07/27] target/lm32: Convert to CPUClass::tlb_fill [PULL,08/27] target/m68k: Convert to CPUClass::tlb_fill [PULL,09/27] target/microblaze: Convert to CPUClass::tlb_fill [PULL,10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only [PULL,11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault [PULL,12/27] target/mips: Convert to CPUClass::tlb_fill [PULL,13/27] target/moxie: Convert to CPUClass::tlb_fill [PULL,14/27] target/nios2: Convert to CPUClass::tlb_fill [PULL,15/27] target/openrisc: Convert to CPUClass::tlb_fill [PULL,16/27] target/ppc: Convert to CPUClass::tlb_fill [PULL,17/27] target/riscv: Convert to CPUClass::tlb_fill [PULL,18/27] target/s390x: Convert to CPUClass::tlb_fill [PULL,19/27] target/sh4: Convert to CPUClass::tlb_fill [PULL,20/27] target/sparc: Convert to CPUClass::tlb_fill [PULL,21/27] target/tilegx: Convert to CPUClass::tlb_fill [PULL,22/27] target/tricore: Convert to CPUClass::tlb_fill [PULL,23/27] target/unicore32: Convert to CPUClass::tlb_fill [PULL,24/27] target/xtensa: Convert to CPUClass::tlb_fill [PULL,25/27] tcg: Use CPUClass::tlb_fill in cputlb.c [PULL,26/27] tcg: Remove CPUClass::handle_mmu_fault [PULL,27/27] tcg: Use tlb_fill probe from tlb_vaddr_to_host

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 58e988b3b1..31f0ecc461 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -474,15 +474,6 @@ static inline void assert_no_pages_locked(void) */ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, hwaddr index, MemTxAttrs attrs); - -/* - * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the - * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must - * be discarded and looked up again (e.g. via tlb_entry()). - */ -void tlb_fill(CPUState *cpu, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - #endif #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f2f618217d..dfcd9ae168 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -855,6 +855,25 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) return ram_addr; } +/* + * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the + * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must + * be discarded and looked up again (e.g. via tlb_entry()). + */ +static void tlb_fill(CPUState *cpu, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + bool ok; + + /* + * This is not a probe, so only valid return is success; failure + * should result in exception + longjmp to the cpu loop. + */ + ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr); + assert(ok); +} + static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 929a217455..5fe9c87912 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -275,12 +275,6 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} #endif /* USER_ONLY */ void alpha_cpu_do_interrupt(CPUState *cs) diff --git a/target/arm/helper.c b/target/arm/helper.c index f1a2b94ddb..e2d5c8e34f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13127,14 +13127,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #endif } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) { /* Implement DC ZVA, which zeroes a fixed-length block of memory. diff --git a/target/cris/helper.c b/target/cris/helper.c index 69464837c8..b5159b8357 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -123,12 +123,6 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit(cs); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void crisv10_cpu_do_interrupt(CPUState *cs) { CRISCPU *cpu = CRIS_CPU(cs); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 5cee0c19b1..0fd3ac6645 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -260,12 +260,6 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, return true; } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType type, int mmu_idx, uintptr_t retaddr) -{ - hppa_cpu_tlb_fill(cs, addr, size, type, mmu_idx, false, retaddr); -} - /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) { diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index 68bf8e3f7c..fa1ead6404 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -700,11 +700,3 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, return true; #endif } - -#if !defined(CONFIG_USER_ONLY) -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/lm32/helper.c b/target/lm32/helper.c index 1db9a5562e..20ea17ba23 100644 --- a/target/lm32/helper.c +++ b/target/lm32/helper.c @@ -44,12 +44,6 @@ bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return true; } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - lm32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { LM32CPU *cpu = LM32_CPU(cs); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 862f955f7b..9fc9e646ff 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -884,14 +884,6 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif - uint32_t HELPER(bitrev)(uint32_t x) { x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a523c77959..ab2ceeb055 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -108,12 +108,6 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mb_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void mb_cpu_do_interrupt(CPUState *cs) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); diff --git a/target/mips/helper.c b/target/mips/helper.c index 3a4917ce7b..9799f2ede1 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -944,12 +944,6 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } #ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) { hwaddr physical; diff --git a/target/moxie/helper.c b/target/moxie/helper.c index 216cef057e..f5c1d4181c 100644 --- a/target/moxie/helper.c +++ b/target/moxie/helper.c @@ -26,12 +26,6 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - moxie_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - void helper_raise_exception(CPUMoxieState *env, int ex) { CPUState *cs = CPU(moxie_env_get_cpu(env)); diff --git a/target/nios2/helper.c b/target/nios2/helper.c index eb2eed7ad3..ffb83fc104 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -311,10 +311,4 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, env->regs[CR_BADADDR] = address; cpu_loop_exit_restore(cs, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - nios2_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 94c65a25fa..a73b12af03 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -178,10 +178,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - openrisc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, 0, retaddr); -} #endif diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index afcca50530..e605efa883 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -3080,9 +3080,3 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, } return true; } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - ppc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2535435260..41d6db41c3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -378,12 +378,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->badaddr = addr; riscv_raise_exception(env, cs->exception_index, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} #endif bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index a4e134bcab..3a467b72c5 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -178,12 +178,6 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit(cs); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - s390_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - static void do_program_interrupt(CPUS390XState *env) { uint64_t mask, addr; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 1517a6152f..fda195e7cb 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -872,11 +872,3 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } cpu_loop_exit_restore(cs, retaddr); } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - superh_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} -#endif diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 2558c08a64..b4bf6faf41 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1924,10 +1924,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, #endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} #endif diff --git a/target/tricore/helper.c b/target/tricore/helper.c index ed184fee3a..a680336850 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -85,12 +85,6 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - static void tricore_cpu_list_entry(gpointer data, gpointer user_data) { ObjectClass *oc = data; diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 13678df4d7..27f218abf0 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -275,12 +275,6 @@ bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); -} - hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { error_report("function uc32_cpu_get_phys_page_debug not " diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5c94f934dd..efb966b3bf 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -305,12 +305,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } } -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, retaddr); -} - void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs,

[PULL,25/27] tcg: Use CPUClass::tlb_fill in cputlb.c

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