From patchwork Thu May 9 06:02:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 163682 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp556147ilr; Wed, 8 May 2019 23:21:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqylmq8q0tDDa1Wu6D5tQSav7UPXFL0bZSHjE1KbO5FwrWs/hgCzvBRmiiNfDym/2Lvkuu8I X-Received: by 2002:a1c:eb07:: with SMTP id j7mr1361627wmh.138.1557382900652; Wed, 08 May 2019 23:21:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557382900; cv=none; d=google.com; s=arc-20160816; b=IQSv/bf96atjNHEKgawvEnLvj6nEvMeFkksVxgqSD7HPaVJkMl2jWi2buV8A0nn6Ih jAmitN+ibWUD7feYsAZKQBHLLB5yWX+BypgAncW5OH2fPxsml2F6FIBrmfiXZnnJAMix qyJU+UJp0YJ7bOzGxDempEhpref10dYXBvU93ZLpz9bwNUc4BhXmuYpo8CHFh/548o1S PN8ZRJXG0n5acaHfXWF9+AUw+uzF+aEwogIk5MEZ0VK8Ewb0vWbcF4LF9vP+2XDGd1EV +kfygD1MiRN1xDtFdyK4rZakT9V76CvSwedkXQAbO+wh9ZdxsdVETaNeCOtlMlBw6yGx jCbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=WBbuMFJPoHwZ9nvC2CuWnBbrsjf1dWxChrYOssiCWu0=; b=qkp8xmVK5QjRVcWQoI4q7D1STj1go2rrpmKCUfIAu99KOoyfSa3IQ4fxE/Lf+Tdosn EruEnbg9EABBOdagcJCjWLvErXUZQRbp45BxTK3paX/8RchkuzAzRnB/HwI+rGl1LzRb ja9QVBKi0a3ZTo2zEQ+SjfMUQX2kchQd9q2VSk0H+dkY6Ff6nZDavGjrQ6XYWIo/0wtB HrjgI2U5fRXQeIBRWu9XoDSO/xx134x4ecjsTr0ckaGa3/T0JzwH/gMarpAH6zSCEtoC fzbvFwGlA0321+Cghox24/5oqGM5rPI/UEWYiRd6WvJAFVdZvlRLMcN+8Z2K2JKPwcZq m3uA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lv1CIGZI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c17si827206wmd.55.2019.05.08.23.21.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 08 May 2019 23:21:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lv1CIGZI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:48850 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOcR1-0006wi-F3 for patch@linaro.org; Thu, 09 May 2019 02:21:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:45121) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hOc9L-0006KM-TJ for qemu-devel@nongnu.org; Thu, 09 May 2019 02:03:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hOc9K-0007IR-6x for qemu-devel@nongnu.org; Thu, 09 May 2019 02:03:23 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40191) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hOc9J-0007HY-Vt for qemu-devel@nongnu.org; Thu, 09 May 2019 02:03:22 -0400 Received: by mail-pg1-x541.google.com with SMTP id d31so629309pgl.7 for ; Wed, 08 May 2019 23:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WBbuMFJPoHwZ9nvC2CuWnBbrsjf1dWxChrYOssiCWu0=; b=lv1CIGZIlqIXI2rxq1Hh06IfQEHfRMsGIVjggqqGQu0VRXNtBIXiKm4EhwMeWR6iQV 4DYkFQVJCHr80oGyYZCvVOoS2c6IhUxF0lO1VaJHglBiLf8Tl6NI+ux/qgennorkM7XF GyiL0GgHQqt3eFuFG4mf8DIeGQ4I3Q8z0IXUdShTJ67BudzsK9Y4s6DYoQqesOT4Ta6E 1D/5QBd+ltxQMKRE7tNK3tio625Tj1iub5WHePaeC67MqHQVYIILx7igfe0Z95InnJ0S XIT9jv3Xa1Q/Mvh3fWjyF9DLZSrXi4z4QKQA9s2l8rIJuCXJ8OZg8aE8Z1wkPKzArD4c LCmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WBbuMFJPoHwZ9nvC2CuWnBbrsjf1dWxChrYOssiCWu0=; b=ijqSIU7SNsS9dZR91hQkscFkR1tlQLNXO1RjJL0xj/0858RHk5n9F8/K/goKMZbxNX V7ZAs0C8iXIEhp7DRl+rXdZx4wkrL7blN/hHksiS99eFn87wqp16CpWwc2B/EQEa1uNx 9sVP4MgqFSumoO6a+hLMvQikUOFpS3p/0Pbz0EykzfUfd6mb/7+OZiiPAXE2gPgV8omE CgW6Mtm5WRaYPdyblLXZlhMqzwwon6yk21mStFGLWRISb9PQtHU+Rac1iNpmkRItYADw kAJ+pz1nQAUhMp5zFu0Y/JxF/sA3PcvlqgCkZ4UrKN7ATyJgfR/OHYK1taJP9TZMpSNF 6ZRA== X-Gm-Message-State: APjAAAVYBE6USDcwua5IWDm0qaOQNBlt88eU0hapsmqu3dCfXvmsgMNj s3HRiQdjuSG6s7yeYb1yG5QM9b9LUMM= X-Received: by 2002:a62:f245:: with SMTP id y5mr2640467pfl.12.1557381800142; Wed, 08 May 2019 23:03:20 -0700 (PDT) Received: from localhost.localdomain (97-113-27-95.tukw.qwest.net. [97.113.27.95]) by smtp.gmail.com with ESMTPSA id n7sm1496109pff.45.2019.05.08.23.03.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 May 2019 23:03:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 May 2019 23:02:43 -0700 Message-Id: <20190509060246.4031-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509060246.4031-1-richard.henderson@linaro.org> References: <20190509060246.4031-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 24/27] target/xtensa: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Max Filippov Signed-off-by: Richard Henderson --- v2: Keep user-only and system tlb_fill separate. --- target/xtensa/cpu.h | 5 +++-- target/xtensa/cpu.c | 5 ++--- target/xtensa/helper.c | 39 ++++++++++++++++++++++++++------------- 3 files changed, 31 insertions(+), 18 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 5d23e1345b..68d89f8faf 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -552,8 +552,9 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) #define ENV_OFFSET offsetof(XtensaCPU, env) -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, - int mmu_idx); +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a54dbe4260..da1236377e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,9 +181,8 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = xtensa_cpu_gdb_read_register; cc->gdb_write_register = xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint = true; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = xtensa_cpu_handle_mmu_fault; -#else + cc->tlb_fill = xtensa_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed = xtensa_cpu_do_transaction_failed; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 5f37f378a3..5c94f934dd 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -240,19 +240,21 @@ void xtensa_cpu_list(void) #ifdef CONFIG_USER_ONLY -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n", - __func__, rw, address, size); + __func__, access_type, address, size); env->sregs[EXCVADDR] = address; - env->sregs[EXCCAUSE] = rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE; + env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ? + STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE); cs->exception_index = EXC_USER; - return 1; + cpu_loop_exit_restore(cs, retaddr); } #else @@ -273,31 +275,42 @@ void xtensa_cpu_do_unaligned_access(CPUState *cs, } } -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; - int ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx, - &paddr, &page_size, &access); + int ret = xtensa_get_physical_addr(env, true, address, access_type, + mmu_idx, &paddr, &page_size, &access); - qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n", - __func__, vaddr, access_type, mmu_idx, paddr, ret); + qemu_log_mask(CPU_LOG_MMU, "%s(%08" VADDR_PRIx + ", %d, %d) -> %08x, ret = %d\n", + __func__, address, access_type, mmu_idx, paddr, ret); if (ret == 0) { tlb_set_page(cs, - vaddr & TARGET_PAGE_MASK, + address & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); + return true; + } else if (probe) { + return false; } else { cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); + HELPER(exception_cause_vaddr)(env, env->pc, ret, address); } } +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + xtensa_cpu_tlb_fill(cs, vaddr, size, access_type, mmu_idx, false, retaddr); +} + void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs,