[v3,04/39] cpu: Define CPUArchState with typedef

Message ID	20190508000641.19090-5-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Tue, 7 May 2019 17:06:06 -0700 Message-Id: <20190508000641.19090-5-richard.henderson@linaro.org> In-Reply-To: <20190508000641.19090-1-richard.henderson@linaro.org> References: <20190508000641.19090-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v3 04/39] cpu: Define CPUArchState with typedef Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg: Move the softmmu tlb to CPUNegativeOffsetState \| expand [v3,00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState [v3,01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc [v3,02/39] tcg: Split out target/arch/cpu-param.h [v3,03/39] tcg: Create struct CPUTLB [v3,04/39] cpu: Define CPUArchState with typedef [v3,05/39] cpu: Define ArchCPU [v3,06/39] cpu: Replace ENV_GET_CPU with env_cpu [v3,07/39] cpu: Introduce env_archcpu [v3,08/39] target/alpha: Use env_cpu, env_archcpu [v3,09/39] target/arm: Use env_cpu, env_archcpu [v3,10/39] target/cris: Reindent mmu.c [v3,11/39] target/cris: Reindent op_helper.c [v3,12/39] target/cris: Use env_cpu, env_archcpu [v3,13/39] target/hppa: Use env_cpu, env_archcpu [v3,14/39] target/i386: Use env_cpu, env_archcpu [v3,15/39] target/lm32: Use env_cpu, env_archcpu [v3,16/39] target/m68k: Use env_cpu, env_archcpu [v3,17/39] target/microblaze: Use env_cpu, env_archcpu [v3,18/39] target/mips: Use env_cpu, env_archcpu [v3,19/39] target/moxie: Use env_cpu, env_archcpu [v3,20/39] target/nios2: Use env_cpu, env_archcpu [v3,21/39] target/openrisc: Use env_cpu, env_archcpu [v3,22/39] target/ppc: Use env_cpu, env_archcpu [v3,23/39] target/riscv: Use env_cpu, env_archcpu [v3,24/39] target/s390x: Use env_cpu, env_archcpu [v3,25/39] target/sh4: Use env_cpu, env_archcpu [v3,26/39] target/sparc: Use env_cpu, env_archcpu [v3,27/39] target/tilegx: Use env_cpu [v3,28/39] target/tricore: Use env_cpu [v3,29/39] target/unicore32: Use env_cpu, env_archcpu [v3,30/39] target/xtensa: Use env_cpu, env_archcpu [v3,31/39] cpu: Move ENV_OFFSET to exec/gen-icount.h [v3,32/39] cpu: Introduce cpu_set_cpustate_pointers [v3,33/39] cpu: Introduce CPUNegativeOffsetState [v3,34/39] cpu: Move icount_decr to CPUNegativeOffsetState [v3,35/39] cpu: Move the softmmu tlb to CPUNegativeOffsetState [v3,36/39] cpu: Remove CPU_COMMON [v3,37/39] tcg/aarch64: Use LDP to load tlb mask+table [v3,38/39] tcg/arm: Use LDRD to load tlb mask+table [v3,39/39] tcg/arm: Remove mostly unreachable tlb special case

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 2ab468ffd6..56d1eade4f 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -26,8 +26,6 @@ #define ALIGNED_ONLY -#define CPUArchState struct CPUAlphaState - /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) @@ -301,6 +299,8 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, #define cpu_list alpha_cpu_list #define cpu_signal_handler cpu_alpha_signal_handler +typedef CPUAlphaState CPUArchState; + #include "exec/cpu-all.h" enum { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca199d1afb..9b4874112f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -29,8 +29,6 @@ /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) -#define CPUArchState struct CPUARMState - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 @@ -3114,6 +3112,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) } } +typedef CPUARMState CPUArchState; + #include "exec/cpu-all.h" /* Bit usage in the TB flags field: bit 31 indicates whether we are diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 3fbe1232ab..94e1a2aed7 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -25,8 +25,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define CPUArchState struct CPUCRISState - #define EXCP_NMI 1 #define EXCP_GURU 2 #define EXCP_BUSFAULT 3 @@ -285,6 +283,8 @@ int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 +typedef CPUCRISState CPUArchState; + #include "exec/cpu-all.h" static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc, diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f96c3a17e4..c9bb16af9b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -31,8 +31,6 @@ basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL -#define CPUArchState struct CPUHPPAState - #define ALIGNED_ONLY #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 @@ -232,6 +230,8 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) #define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) #define ENV_OFFSET offsetof(HPPACPU, env) +typedef CPUHPPAState CPUArchState; + #include "exec/cpu-all.h" static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e53dbdeee5..2ccd796e9b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1,4 +1,3 @@ - /* * i386 virtual CPU header * @@ -44,8 +43,6 @@ #define ELF_MACHINE_UNAME "i686" #endif -#define CPUArchState struct CPUX86State - enum { R_EAX = 0, R_ECX = 1, @@ -1753,6 +1750,8 @@ static inline target_long lshift(target_long x, int n) /* translate.c */ void tcg_x86_init(void); +typedef CPUX86State CPUArchState; + #include "exec/cpu-all.h" #include "svm.h" diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index 79852dda5a..bd23c39d7a 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -24,9 +24,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define CPUArchState struct CPULM32State - -struct CPULM32State; typedef struct CPULM32State CPULM32State; static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) @@ -258,6 +255,8 @@ bool lm32_cpu_do_semihosting(CPUState *cs); int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); +typedef CPULM32State CPUArchState; + #include "exec/cpu-all.h" static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc, diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index bad85174ca..2f92972dca 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -25,8 +25,6 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" -#define CPUArchState struct CPUM68KState - #define OS_BYTE 0 #define OS_WORD 1 #define OS_LONG 2 @@ -536,6 +534,8 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size); +typedef CPUM68KState CPUArchState; + #include "exec/cpu-all.h" /* TB flags */ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 406dc0b5a3..ac3e785927 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -25,9 +25,6 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#define CPUArchState struct CPUMBState - -struct CPUMBState; typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" @@ -367,6 +364,8 @@ static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); +typedef CPUMBState CPUArchState; + #include "exec/cpu-all.h" static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index b97b018399..522d2ebadc 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -3,8 +3,6 @@ #define ALIGNED_ONLY -#define CPUArchState struct CPUMIPSState - #include "qemu-common.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" @@ -13,8 +11,6 @@ #define TCG_GUEST_DEFAULT_MO (0) -struct CPUMIPSState; - typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; /* MSA Context */ @@ -1094,6 +1090,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) return hflags_mmu_index(env->hflags); } +typedef CPUMIPSState CPUArchState; + #include "exec/cpu-all.h" /* Memory access type : diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index fcb2ea76b7..dcc319adf6 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -23,8 +23,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" -#define CPUArchState struct CPUMoxieState - #define MOXIE_EX_DIV0 0 #define MOXIE_EX_BAD 1 #define MOXIE_EX_IRQ 2 @@ -119,6 +117,8 @@ static inline int cpu_mmu_index(CPUMoxieState *env, bool ifetch) return 0; } +typedef CPUMoxieState CPUArchState; + #include "exec/cpu-all.h" static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc, diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index b737b23fc5..915ddd386f 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qom/cpu.h" -#define CPUArchState struct CPUNios2State - -struct CPUNios2State; typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" @@ -247,6 +244,8 @@ static inline int cpu_interrupts_enabled(CPUNios2State *env) return env->regs[CR_STATUS] & CR_STATUS_PIE; } +typedef CPUNios2State CPUArchState; + #include "exec/cpu-all.h" static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bf8a354307..e327c81703 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "qom/cpu.h" -#define CPUArchState struct CPUOpenRISCState - /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; @@ -364,6 +362,8 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU +typedef CPUOpenRISCState CPUArchState; + #include "exec/cpu-all.h" #define TB_FLAGS_SM SR_SM diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e86f1650d5..2bf526403e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -34,8 +34,6 @@ #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 -#define CPUArchState struct CPUPPCState - #if defined(TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 #else @@ -1378,6 +1376,8 @@ void ppc_compat_add_property(Object *obj, const char *name, Error **errp); #endif /* defined(TARGET_PPC64) */ +typedef CPUPPCState CPUArchState; + #include "exec/cpu-all.h" /*****************************************************************************/ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8f480de324..0f7124132e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,8 +27,6 @@ #define TCG_GUEST_DEFAULT_MO 0 -#define CPUArchState struct CPURISCVState - #define TYPE_RISCV_CPU "riscv-cpu" #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -325,6 +323,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +typedef CPURISCVState CPUArchState; + #include "exec/cpu-all.h" #endif /* RISCV_CPU_H */ diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 3a82ea53e1..5ca53f48f8 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,13 +28,9 @@ #define ELF_MACHINE_UNAME "S390X" -#define CPUArchState struct CPUS390XState - /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) -#include "exec/cpu-all.h" - #define TARGET_INSN_START_EXTRA_WORDS 1 #define MMU_MODE0_SUFFIX _primary @@ -797,4 +793,8 @@ void s390_init_sigp(void); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); +typedef CPUS390XState CPUArchState; + +#include "exec/cpu-all.h" + #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 75d8e1b235..4df8cb0471 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -36,8 +36,6 @@ #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) -#define CPUArchState struct CPUSH4State - #define SR_MD 30 #define SR_RB 29 #define SR_BL 28 @@ -281,6 +279,8 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) } } +typedef CPUSH4State CPUArchState; + #include "exec/cpu-all.h" /* Memory access type */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b11a1bd3fa..620bb74329 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -14,8 +14,6 @@ #define TARGET_DPREGS 32 #endif -#define CPUArchState struct CPUSPARCState - /*#define EXCP_INTERRUPT 0x100*/ /* trap definitions */ @@ -730,6 +728,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) #endif } +typedef CPUSPARCState CPUArchState; + #include "exec/cpu-all.h" #ifdef TARGET_SPARC64 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 429a6c6b43..2fbf14d508 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -23,8 +23,6 @@ #include "qemu-common.h" #include "exec/cpu-defs.h" -#define CPUArchState struct CPUTLGState - /* TILE-Gx common register alias */ #define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */ #define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */ @@ -152,6 +150,8 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env) /* TILE-Gx memory attributes */ #define MMU_USER_IDX 0 /* Current memory operation is in user mode */ +typedef CPUTLGState CPUArchState; + #include "exec/cpu-all.h" void tilegx_tcg_init(void); diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 79f5068c25..39376e4e1e 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -25,10 +25,6 @@ #include "exec/cpu-defs.h" #include "tricore-defs.h" -#define CPUArchState struct CPUTriCoreState - -struct CPUTriCoreState; - struct tricore_boot_info; typedef struct tricore_def_t tricore_def_t; @@ -382,7 +378,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) return 0; } - +typedef CPUTriCoreState CPUArchState; #include "exec/cpu-all.h" diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index e15088eb91..6d7439b368 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -16,8 +16,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define CPUArchState struct CPUUniCore32State - typedef struct CPUUniCore32State { /* Regs for current mode. */ uint32_t regs[32]; @@ -153,6 +151,8 @@ static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch) return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0; } +typedef CPUUniCore32State CPUArchState; + #include "exec/cpu-all.h" #define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 970c223cf7..979a5fde7e 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -38,8 +38,6 @@ /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) -#define CPUArchState struct CPUXtensaState - enum { /* Additional instructions */ XTENSA_OPTION_CODE_DENSITY, @@ -788,6 +786,8 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, } } +typedef CPUXtensaState CPUArchState; + #include "exec/cpu-all.h" #endif

[v3,04/39] cpu: Define CPUArchState with typedef

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