| Message ID | 20190501050536.15580-23-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg vector improvements | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > tcg/aarch64/tcg-target.h | 2 +- > tcg/aarch64/tcg-target.inc.c | 6 ++++++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h > index 21d06d928c..e43554c3c7 100644 > --- a/tcg/aarch64/tcg-target.h > +++ b/tcg/aarch64/tcg-target.h > @@ -132,7 +132,7 @@ typedef enum { > #define TCG_TARGET_HAS_orc_vec 1 > #define TCG_TARGET_HAS_not_vec 1 > #define TCG_TARGET_HAS_neg_vec 1 > -#define TCG_TARGET_HAS_abs_vec 0 > +#define TCG_TARGET_HAS_abs_vec 1 > #define TCG_TARGET_HAS_shi_vec 1 > #define TCG_TARGET_HAS_shs_vec 0 > #define TCG_TARGET_HAS_shv_vec 1 > diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c > index 61c2dbbff2..e7f8d96e21 100644 > --- a/tcg/aarch64/tcg-target.inc.c > +++ b/tcg/aarch64/tcg-target.inc.c > @@ -554,6 +554,7 @@ typedef enum { > I3617_CMGE0 = 0x2e208800, > I3617_CMLE0 = 0x2e20a800, > I3617_NOT = 0x2e205800, > + I3617_ABS = 0x0e20b800, > I3617_NEG = 0x2e20b800, > > /* System instructions. */ > @@ -2209,6 +2210,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, > case INDEX_op_neg_vec: > tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); > break; > + case INDEX_op_abs_vec: > + tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); > + break; > case INDEX_op_and_vec: > tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2); > break; > @@ -2320,6 +2324,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) > case INDEX_op_andc_vec: > case INDEX_op_orc_vec: > case INDEX_op_neg_vec: > + case INDEX_op_abs_vec: > case INDEX_op_not_vec: > case INDEX_op_cmp_vec: > case INDEX_op_shli_vec: > @@ -2563,6 +2568,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) > return &w_w_w; > case INDEX_op_not_vec: > case INDEX_op_neg_vec: > + case INDEX_op_abs_vec: > case INDEX_op_shli_vec: > case INDEX_op_shri_vec: > case INDEX_op_sari_vec: -- Alex Bennée
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 21d06d928c..e43554c3c7 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -132,7 +132,7 @@ typedef enum { #define TCG_TARGET_HAS_orc_vec 1 #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 61c2dbbff2..e7f8d96e21 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -554,6 +554,7 @@ typedef enum { I3617_CMGE0 = 0x2e208800, I3617_CMLE0 = 0x2e20a800, I3617_NOT = 0x2e205800, + I3617_ABS = 0x0e20b800, I3617_NEG = 0x2e20b800, /* System instructions. */ @@ -2209,6 +2210,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_neg_vec: tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); break; + case INDEX_op_abs_vec: + tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); + break; case INDEX_op_and_vec: tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2); break; @@ -2320,6 +2324,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_andc_vec: case INDEX_op_orc_vec: case INDEX_op_neg_vec: + case INDEX_op_abs_vec: case INDEX_op_not_vec: case INDEX_op_cmp_vec: case INDEX_op_shli_vec: @@ -2563,6 +2568,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &w_w_w; case INDEX_op_not_vec: case INDEX_op_neg_vec: + case INDEX_op_abs_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec:
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) -- 2.17.1