From patchwork Wed Apr 3 03:43:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161666 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2519517jan; Tue, 2 Apr 2019 20:59:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdjSroE0sxYvJ1uvy+EdSsmKb9SZq2TP+cx7DEgpEndIWRJX3YZaiEqre9+lQMYpwlowCZ X-Received: by 2002:a25:1954:: with SMTP id 81mr61623385ybz.120.1554263951207; Tue, 02 Apr 2019 20:59:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554263951; cv=none; d=google.com; s=arc-20160816; b=iBbZ/8YXago9zZJc6kC12wUo4rIWzG1egaf0O4SP4y9D+NbBXnhgWeGIRFViMGgGQN 9b5tspfDvacqrnaP9f/wQlqWa28/19pSn6n/ogL8pmzH23CYtRtsnjIPDdZouypVSgAO Evoz004NkpzzjVSXsy+fLZDiq9ZdUHwbNZLAAzTfEOusPf6m0YbUdL9k5Vk0ujrFiXQY 8yvG7tAWRobk8YKH+wTOqAQaI1DFIC8tVtOTd75nLEn5ddw/mKNv9TswXkId/7MzPyGo ctlZ7pbJAzJUQdFL4m+bL0DDC5S6xF8fHNQ30PSeU9OEKmbLLrcGIGFP0yhecrbGX4we 85rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=UbBnQKm5Hcwo0TN6/Oh/RTv+4uaUVdLp1efEYGx2g/M=; b=rwYteqp2lRyCq4ITwddkMp8Pg5Qztu0KP1rSTkm4GDrnAcxNffrTnln7RgnGLkOMmP 488lx8GJm94WFpn5UmWWeI3ELJemBvjSY9NG9DL6doJ8Kn2Rjqcg+OkBaIIUyUQ5y4ar cMfQZ2ERpF6wIjY5vz+CfxuQkz73YbRmAoYCZEuLp6ILvFSeDsH6N2FANHJNiUnfQT1U qutbzAX1K2/M3f2eAbfROORxilTpxDW6W4u1C8MnIm7vf6kj8yaiL2XM6Q0JB1cw4qJP rCavLOYD8Fyl0gKw1+8MimGCZNVAw+VgJdchqzy0YTfuOWqt42JMQjor3EWVtaF5+7bv Gyug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sF932MCp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p193si9079153ywg.40.2019.04.02.20.59.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 02 Apr 2019 20:59:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sF932MCp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:54969 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBX3O-0007GL-Kc for patch@linaro.org; Tue, 02 Apr 2019 23:59:10 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBWpW-0003DV-5a for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBWpU-0000My-Ut for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:50 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:42281) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hBWpU-0000Lf-LG for qemu-devel@nongnu.org; Tue, 02 Apr 2019 23:44:48 -0400 Received: by mail-pg1-x52c.google.com with SMTP id p6so7576673pgh.9 for ; Tue, 02 Apr 2019 20:44:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UbBnQKm5Hcwo0TN6/Oh/RTv+4uaUVdLp1efEYGx2g/M=; b=sF932MCpL3jylarTPiVtzO2oED3ow7ntfIs8tkzwUA6+x1VKztScpQJ/CR0bCqkSje QBHjVOjzUbg56H/c8OfXAhQ5siD9h5fnbt48HPgxdcUy0o7A6cgY59raU7IE452PYGdL dWiYptO+lxKrSNF3yaq5WFDn6ie8GLM7fq/1DmIrEI8UX+rx+QpCndgEeYLuFk98gTHg wRsNmJKoD03dcl7EJa93c4Pz3M2K8l6Ipe2m/UfrrlbKoCeCcBLCvIgGfXc51djUs8hz CIZJugCdLxMRG/qiMx26kcoK6mk+63f7snH4op6KEF+OZm6X/fkna7cz/ucgspDr6Lrh bSNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UbBnQKm5Hcwo0TN6/Oh/RTv+4uaUVdLp1efEYGx2g/M=; b=UaJt3zz7UF0WpjaeNJn0dy5nrLkFtaydj1p3aDIaaxqGMrg4MgR7dTFuC5QN+MbXoL U7Ls5tWHuRW7U//XhSK7XwgWcQNP1QkX8RqucmwnvP0NcIFpNQSkpYwMU9l6TBstvg/I aPNk29q/eLPedYtx/51Z5fykRnNRuhlaa0aokGPe05Rc3mNvJLchSEyt2OdDMAmRhLeO FrUrWWb+RLdpiYqfn7GhtOyIpmkIB/TYbk63tw8Ww+BCz50pgmn/b7xBI8OgFlx4Exb+ +/CX0O0JqvCNclxJhMVzuLjf4eKHAM4gon5bKnGPAMyr24swKkzXWK53Lm0N4NyZbk2q 8+Xw== X-Gm-Message-State: APjAAAVAn+9rwGuQM+wBI+NvQITBesJqJVnfZoXH1IwAvr5E603TpWKz jQ3/SbvYY1Wask0ZCI1gIVUEaraU1/rttA== X-Received: by 2002:a63:cf0d:: with SMTP id j13mr35961684pgg.34.1554263087281; Tue, 02 Apr 2019 20:44:47 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id z6sm26753214pgo.31.2019.04.02.20.44.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Apr 2019 20:44:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2019 10:43:54 +0700 Message-Id: <20190403034358.21999-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org> References: <20190403034358.21999-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52c Subject: [Qemu-devel] [PATCH 22/26] target/unicore32: Convert to CPUClass::tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Guan Xuetao Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Guan Xuetao Signed-off-by: Richard Henderson --- target/unicore32/cpu.h | 5 +++-- target/unicore32/cpu.c | 5 +---- target/unicore32/helper.c | 23 ----------------------- target/unicore32/op_helper.c | 14 -------------- target/unicore32/softmmu.c | 19 +++++++++++++++---- 5 files changed, 19 insertions(+), 47 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 735d3ae9dc..dfec908cad 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -179,8 +179,9 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc } } -int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void uc32_translate_init(void); void switch_mode(CPUUniCore32State *, int); diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 2b49d1ca40..3f57c508a0 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -138,11 +138,8 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt; cc->dump_state = uc32_cpu_dump_state; cc->set_pc = uc32_cpu_set_pc; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault; -#else + cc->tlb_fill = uc32_cpu_tlb_fill; cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; -#endif cc->tcg_initialize = uc32_translate_init; dc->vmsd = &vmstate_uc32_cpu; } diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index a5ff2ddb74..0d4914b48d 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -215,29 +215,6 @@ void helper_cp1_putc(target_ulong x) } #endif -#ifdef CONFIG_USER_ONLY -void switch_mode(CPUUniCore32State *env, int mode) -{ - UniCore32CPU *cpu = uc32_env_get_cpu(env); - - if (mode != ASR_MODE_USER) { - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); - } -} - -void uc32_cpu_do_interrupt(CPUState *cs) -{ - cpu_abort(cs, "NO interrupt in user mode\n"); -} - -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) -{ - cpu_abort(cs, "NO mmu fault in user mode\n"); - return 1; -} -#endif - bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index e0a15882d3..797ba60dc9 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -242,17 +242,3 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } - -#ifndef CONFIG_USER_ONLY -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = uc32_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (unlikely(ret)) { - /* now we have a real cpu fault */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 00c7e0d028..13678df4d7 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -215,8 +215,9 @@ do_fault: return code; } -int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int access_type, int mmu_idx) +bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { UniCore32CPU *cpu = UNICORE32_CPU(cs); CPUUniCore32State *env = &cpu->env; @@ -257,7 +258,11 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); - return 0; + return true; + } + + if (probe) { + return false; } env->cp0.c3_faultstatus = ret; @@ -267,7 +272,13 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, } else { cs->exception_index = UC32_EXCP_DTRAP; } - return ret; + cpu_loop_exit_restore(cs, retaddr); +} + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + uc32_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)