[05/97] target/arm: Fix typo in helper_sve_ld1hss_r

Message ID	20190401210011.16009-6-mdroth@linux.vnet.ibm.com
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Gateway: Authorized Use Only! Violators will be prosecuted for <qemu-devel@nongnu.org> from <mdroth@linux.vnet.ibm.com>; Mon, 1 Apr 2019 22:02:50 +0100 Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 1 Apr 2019 22:02:47 +0100 From: Michael Roth <mdroth@linux.vnet.ibm.com> To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 15:58:39 -0500 In-Reply-To: <20190401210011.16009-1-mdroth@linux.vnet.ibm.com> References: <20190401210011.16009-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Message-Id: <20190401210011.16009-6-mdroth@linux.vnet.ibm.com> Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 05/97] target/arm: Fix typo in helper_sve_ld1hss_r Precedence: list Cc: Peter Maydell <peter.maydell@linaro.org>, Richard Henderson <richard.henderson@linaro.org>, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	[01/97] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw \| expand [01/97] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw [02/97] target/arm: Fix typo in do_sat_addsub_64 [03/97] target/arm: Reorganize SVE WHILE [04/97] target/arm: Fix typo in helper_sve_movz_d [05/97] target/arm: Fix typo in helper_sve_ld1hss_r [06/97] target/arm: Fix sign-extension in sve do_ldr/do_str [07/97] target/arm: Fix offset for LD1R instructions [08/97] target/arm: Fix offset scaling for LD_zprr and ST_zprr [09/97] target/arm: Reformat integer register dump [10/97] target/arm: Dump SVE state if enabled [11/97] target/arm: Add sve-max-vq cpu property to -cpu max [13/97] target/arm: Adjust FPCR_MASK for FZ16 [14/97] target/arm: Ignore float_flag_input_denormal from fp_status_f16 [15/97] target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h [16/97] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half [44/97] target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs [49/97] virt: Suppress external aborts on virt-2.10 and earlier [52/97] target/arm: Correct condition for v8M callee stack push [80/97] linux-user: make pwrite64/pread64(fd, NULL, 0, offset) return 0 [82/97] exec.c: Don't reallocate IOMMUNotifiers that are in use

Message ID

20190401210011.16009-6-mdroth@linux.vnet.ibm.com

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From: Michael Roth <mdroth@linux.vnet.ibm.com>
To: qemu-devel@nongnu.org
Date: Mon,  1 Apr 2019 15:58:39 -0500
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Subject: [Qemu-devel] [PATCH 05/97] target/arm: Fix typo in
	helper_sve_ld1hss_r
Precedence: list
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Richard Henderson <richard.henderson@linaro.org>, qemu-stable@nongnu.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
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Series

[01/97] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw | expand

Commit Message

Michael Roth April 1, 2019, 8:58 p.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>


Cc: qemu-stable@nongnu.org (3.0.1)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

(cherry picked from commit 573ec0fe40b9a412085ac7dfb41975a0fc2b28dd)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

---
 target/arm/sve_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.1

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index c3cbec9cf5..e03f954a26 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -4045,7 +4045,7 @@  DO_LD1(sve_ld1bdu_r, cpu_ldub_data_ra, uint64_t, uint8_t, )
 DO_LD1(sve_ld1bds_r, cpu_ldsb_data_ra, uint64_t, int8_t, )
 
 DO_LD1(sve_ld1hsu_r, cpu_lduw_data_ra, uint32_t, uint16_t, H1_4)
-DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int8_t, H1_4)
+DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int16_t, H1_4)
 DO_LD1(sve_ld1hdu_r, cpu_lduw_data_ra, uint64_t, uint16_t, )
 DO_LD1(sve_ld1hds_r, cpu_ldsw_data_ra, uint64_t, int16_t, )

[05/97] target/arm: Fix typo in helper_sve_ld1hss_r

Commit Message

Patch