From patchwork Mon Apr 1 20:58:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 161573 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp942861jan; Mon, 1 Apr 2019 14:09:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqzokmAZ3BJ75tu1V+zB//Qo8c2tqm5z6LUjIz440HH/ldXJBuGD3IiGQH+MNUzV6PzgFzvn X-Received: by 2002:a81:58a:: with SMTP id 132mr1788967ywf.460.1554152965360; Mon, 01 Apr 2019 14:09:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554152965; cv=none; d=google.com; s=arc-20160816; b=Ao7XO/dupnc6IHTdZ6N2ceUUsi80JXvolQKuQBGMLJf9KRCAIsoQ95RGqfE1B2udh1 8qIZ5+2qW90YVCre7TwrrdW7WQAaDgCJNeYVIzzp6Kb8r9KxaOvmtwgdegzT+WD1hYA/ 9uAIEc4xJ+/PUGtB5ikjw2hpB41QootJMYFNeWmxx8DPNCENuEfu4WkG9hjOVW+i5JQA RIYwKTsHqYgbYkhtaKLjqKtMTGk4g75iEst2Fdgi8IlnGYJ/3AolQkzPOxG2GVCrEEB/ wbNVEBtlOJxRcej/FObeeMiEnl/GnvEuWFG7HHeCk0Hgszxmnv+cS2I+4V/e3GcSGtxl pazg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:message-id:mime-version:references :in-reply-to:date:to:from; bh=EGhK6SVZ0icXAuRmfJw45YwFZ2uq1zyhxUVAnOowlLg=; b=utJcE7UeT0a89KaT7D2Y2iKLdvFsr9EUAo3eRLMwzW1HKdgPGs7vLd70JNMhJ2y57X cg+40t5R1GLgmHTGi38HV1e34VDyR5JpaHWX+JpqSSZToopBmn3VsZdoJg3eWzJddxz9 kBGYrUnxl0UzWljCHoLugiJ0M/hiDST2mlKKhNg43HjhsVfVPRzyHiCbC6g2Y+TDiT4M tiTToF03fZZIKh0jSBVga5HWc8R2rHxpEX0nFLrolsZNtg01OOgR/WgsLhnoK47NX8RU V+oKFgAOrTbByc/suRKtGjA/emjZ+yxM5tOpYlSocc1P3TnmT+Egwe72Ed409PosCZC0 ReCA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t206si6611519yba.2.2019.04.01.14.09.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 01 Apr 2019 14:09:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ibm.com Received: from localhost ([127.0.0.1]:39484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hB4BI-0007Wj-PV for patch@linaro.org; Mon, 01 Apr 2019 17:09:24 -0400 Received: from eggs.gnu.org ([209.51.188.92]:40444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hB43x-0000oe-IW for qemu-devel@nongnu.org; Mon, 01 Apr 2019 17:01:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hB43u-00032z-7e for qemu-devel@nongnu.org; Mon, 01 Apr 2019 17:01:49 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:46146) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hB43t-00030h-KN for qemu-devel@nongnu.org; Mon, 01 Apr 2019 17:01:46 -0400 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x31KrUhh087134 for ; Mon, 1 Apr 2019 17:01:42 -0400 Received: from e13.ny.us.ibm.com (e13.ny.us.ibm.com [129.33.205.203]) by mx0a-001b2d01.pphosted.com with ESMTP id 2rksvqgykj-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 01 Apr 2019 17:01:41 -0400 Received: from localhost by e13.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 1 Apr 2019 22:01:40 +0100 Received: from b01cxnp22034.gho.pok.ibm.com (9.57.198.24) by e13.ny.us.ibm.com (146.89.104.200) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 1 Apr 2019 22:01:37 +0100 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x31L1a3J23527670 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 1 Apr 2019 21:01:36 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 083F5B2064; Mon, 1 Apr 2019 21:01:36 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D4CA0B2066; Mon, 1 Apr 2019 21:01:35 +0000 (GMT) Received: from localhost (unknown [9.80.94.43]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 1 Apr 2019 21:01:35 +0000 (GMT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 15:58:45 -0500 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401210011.16009-1-mdroth@linux.vnet.ibm.com> References: <20190401210011.16009-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19040121-0064-0000-0000-000003C5171A X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010857; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000283; SDB=6.01182941; UDB=6.00619269; IPR=6.00963683; MB=3.00026249; MTD=3.00000008; XFM=3.00000015; UTC=2019-04-01 21:01:38 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19040121-0065-0000-0000-00003CEA806B Message-Id: <20190401210011.16009-12-mdroth@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-01_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1904010135 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x31KrUhh087134 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH 11/97] target/arm: Add sve-max-vq cpu property to -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This allows the default (and maximum) vector length to be set from the command-line. Which is extraordinarily helpful in debugging problems depending on vector length without having to bake knowledge of PR_SET_SVE_VL into every guest binary. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée Tested-by: Alex Bennée Signed-off-by: Peter Maydell (cherry picked from commit adf92eab90e3f5f34c285da6d14d48952b7a8e72) Signed-off-by: Michael Roth --- linux-user/syscall.c | 19 +++++++++++++------ target/arm/cpu.c | 6 +++--- target/arm/cpu.h | 3 +++ target/arm/cpu64.c | 29 +++++++++++++++++++++++++++++ target/arm/helper.c | 7 +++++-- 5 files changed, 53 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index dfc851cc35..5a4af76c03 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10848,15 +10848,22 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, #endif #ifdef TARGET_AARCH64 case TARGET_PR_SVE_SET_VL: - /* We cannot support either PR_SVE_SET_VL_ONEXEC - or PR_SVE_VL_INHERIT. Therefore, anything above - ARM_MAX_VQ results in EINVAL. */ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or + * PR_SVE_VL_INHERIT. Note the kernel definition + * of sve_vl_valid allows for VQ=512, i.e. VL=8192, + * even though the current architectural maximum is VQ=16. + */ ret = -TARGET_EINVAL; if (arm_feature(cpu_env, ARM_FEATURE_SVE) - && arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) { + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { CPUARMState *env = cpu_env; - int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; - int vq = MAX(arg2 / 16, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + uint32_t vq, old_vq; + + old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, cpu->sve_max_vq); if (vq < old_vq) { aarch64_sve_narrow_vq(env, vq); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 64a8005a4b..b25898ed4c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -168,9 +168,9 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |= CPTR_EZ; /* with maximum vector length */ - env->vfp.zcr_el[1] = ARM_MAX_VQ - 1; - env->vfp.zcr_el[2] = ARM_MAX_VQ - 1; - env->vfp.zcr_el[3] = ARM_MAX_VQ - 1; + env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; + env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; + env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e310ffc29d..9526ed27cb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -857,6 +857,9 @@ struct ARMCPU { /* Used to synchronize KVM and QEMU in-kernel device levels */ uint8_t device_irq_level; + + /* Used to set the maximum vector length the cpu will support. */ + uint32_t sve_max_vq; }; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d0581d59d8..800bff780e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,7 @@ #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "qapi/visitor.h" static inline void set_feature(CPUARMState *env, int feature) { @@ -217,6 +218,29 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + visit_type_uint32(v, name, &cpu->sve_max_vq, errp); +} + +static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + Error *err = NULL; + + visit_type_uint32(v, name, &cpu->sve_max_vq, &err); + + if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) { + error_setg(&err, "unsupported SVE vector length"); + error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n", + ARM_MAX_VQ); + } + error_propagate(errp, err); +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -253,6 +277,10 @@ static void aarch64_max_initfn(Object *obj) cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ #endif + + cpu->sve_max_vq = ARM_MAX_VQ; + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, + cpu_max_set_sve_vq, NULL, NULL, &error_fatal); } } @@ -405,6 +433,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) uint64_t pmask; assert(vq >= 1 && vq <= ARM_MAX_VQ); + assert(vq <= arm_env_get_cpu(env)->sve_max_vq); /* Zap the high bits of the zregs. */ for (i = 0; i < 32; i++) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 66afb08ee0..c24c66d43e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12408,9 +12408,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, zcr_len = 0; } else { int current_el = arm_current_el(env); + ARMCPU *cpu = arm_env_get_cpu(env); - zcr_len = env->vfp.zcr_el[current_el <= 1 ? 1 : current_el]; - zcr_len &= 0xf; + zcr_len = cpu->sve_max_vq - 1; + if (current_el <= 1) { + zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + } if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); }