| Message ID | 20190328230404.12909-36-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Move the softmmu tlb to CPUNegativeOffsetState | expand |
On Thu, 28 Mar 2019 at 23:29, Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/aarch64/tcg-target.inc.c | 9 +++------ > 1 file changed, 3 insertions(+), 6 deletions(-) > > diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c > index ac765137ae..979efbcfe4 100644 > --- a/tcg/aarch64/tcg-target.inc.c > +++ b/tcg/aarch64/tcg-target.inc.c > @@ -1463,14 +1463,11 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, > tcg_insn_unit **label_ptr, int mem_index, > bool is_read) > { > - int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); > - int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); > - int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); > unsigned a_bits = get_alignment_bits(opc); > unsigned s_bits = opc & MO_SIZE; > unsigned a_mask = (1u << a_bits) - 1; > unsigned s_mask = (1u << s_bits) - 1; > - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0, x3; > + TCGReg x3; > TCGType mask_type; > uint64_t compare_mask; > > @@ -1478,8 +1475,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, > ? TCG_TYPE_I64 : TCG_TYPE_I32); > > /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ The field names in this comment are out of date, I think ? > - tcg_out_ld(s, mask_type, TCG_REG_X0, mask_base, mask_ofs); > - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, table_base, table_ofs); > + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, > + TLB_MASK_TABLE_OFS(mem_index), 1, 0); Can we have a compile time assert somewhere that the mask and table fields are at the offsets in CPUTLBDescFast that we expect them to be? thanks -- PMM
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index ac765137ae..979efbcfe4 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1463,14 +1463,11 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { - int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); unsigned a_bits = get_alignment_bits(opc); unsigned s_bits = opc & MO_SIZE; unsigned a_mask = (1u << a_bits) - 1; unsigned s_mask = (1u << s_bits) - 1; - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0, x3; + TCGReg x3; TCGType mask_type; uint64_t compare_mask; @@ -1478,8 +1475,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, ? TCG_TYPE_I64 : TCG_TYPE_I32); /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, mask_type, TCG_REG_X0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, table_base, table_ofs); + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); /* Extract the TLB index from the address into X0. */ tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64,
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/aarch64/tcg-target.inc.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) -- 2.17.1