From patchwork Thu Mar 28 23:03:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 161340 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1329003jan; Thu, 28 Mar 2019 16:27:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqxFfOtC0a72WjTmCyeCQllm3B42qMS9fZ6IQpUBgGIDjPrdAyyLsw1o2J0kYfKUc4HDzy26 X-Received: by 2002:a5e:c204:: with SMTP id v4mr32628513iop.252.1553815630534; Thu, 28 Mar 2019 16:27:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553815630; cv=none; d=google.com; s=arc-20160816; b=Co/LlVffELxzWmCswqWyiUvVEdxZwKS54moBX2j3vJ4JUqKcQtH8qyuOsKR/Q4Mg4X YsvpzA9pPARnGeVNWUBoqkYsYHXsKptmfQnjZMj9Lgkf//enyL7Jd4gEo0T0OeafAUsu o0xxGDqCqHgap7m6ayxBPffgpJifTjgWcWYrlW0+IM0l1BuMW2IPQAPjFEVRKY4980/x xvEg/nuV8Rh09Nwp+d/gufUj0pU4BIzHXsAWYu2WUqiYbyDEs6TPjyhIsoApKt/Ih5qU Wnlykyc4DJHh3snAZTECFZjar0I/uTtKHnco7xAVa5gnUDfzT6BS11DVkbARiTmSfK9Y RIvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=h/JYHJOvhKp/F4IlZ+qSqMSkehj6Zo7FJda3RsVFFe0=; b=rDYEmD/P/ZiWLKNMuWPOI+Q6/k4ohj07uNFV22kY1Yxh8ybq4SPm5gK0HDOQTrYvEB FUfMcbxdWiEe0fmicZ5MVDpQTsmJG2KZpLbGqSP6c9K2+OeIdhJfn4XPAmuB+jqYFhHv WBT2395vf0uO5iE3qJrqg8A73dFGFU6f0yinqZDOi5AoOJptOHeDG3k4W5+eYc+FKvXC roZ7l5/GL1EuDU10YwSwxOKIaV7Jt3VqxqHnxictFKgxRkyxHBCu4zhGfNCYzpR75IAq cQ/sibwYRGAEMEkLDonakhWwbUoew2oHfi5b6Paci/hgcNk9Ea6IoVMz7c1D9Ib49KHV LQZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V8BzuRzZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e10si129451jab.117.2019.03.28.16.27.10 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 28 Mar 2019 16:27:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V8BzuRzZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:43256 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eQP-0007tj-RP for patch@linaro.org; Thu, 28 Mar 2019 19:27:09 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h9eKm-0001my-W0 for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:21:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h9e4z-0003EM-KI for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:05:04 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:42611) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h9e4s-0003BU-Cq for qemu-devel@nongnu.org; Thu, 28 Mar 2019 19:04:56 -0400 Received: by mail-pf1-x441.google.com with SMTP id r15so74573pfn.9 for ; Thu, 28 Mar 2019 16:04:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=h/JYHJOvhKp/F4IlZ+qSqMSkehj6Zo7FJda3RsVFFe0=; b=V8BzuRzZ5icf7Oj7LCpWpJNLwjHkT04CyOeInE7ImetCrDQ6/EISevnLUlEIIXXk4R 73hhn5xSPo+466wrvn/Um/9KKzSCZs17soMp5U76uzCTyc3rk7fVJvllv9NXmJpJIp0i Rx6rSFHpXDs8h8KP28M2nQgrgyBY+ZCh8GyzxEVv5RBJwyT4e/EmwFoobVFd+grMYS1P NmIygFBS8rEVgGWvyXGfrUXm6gIUtAT2PwszgmeIrYXqKIBJ5YnP2CFRs+nkN3LQAzfw 98DC5jrzu4CLMIjj6QXkOWuoZ8bPCNvSbFxYCcpTBw7MEmhHeu1vlqmeIAblEhfzX9dU bHxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=h/JYHJOvhKp/F4IlZ+qSqMSkehj6Zo7FJda3RsVFFe0=; b=KGJ/Ct7LpdZgWUxX/+uxFywAG5ZsNKvlCCgOoJC1Ix7E5DpoVPTWsj4tZSvuVVBsnN eDIBXMBAsxm8cqlim2inVLLi8ohNm8mxLk54gUhbfoNFaKPpQMFFOM9f0VUEtEENpBbb 3OZqHBD0MfKGHJhQecHbW53kZ6uGMqrCZOglTgAJpnqaFglMB6X7IPyBTO0sOlJHM3nh tco9Mey0YoVWHTS4PbOiZhLZVDmcSAxUlew5pjb2MNjGTGkCydXR+y5XePUExX5ZHpOS hpkh+DZ31gBqbgSrNTCRznXd0Js89Mma4iYDKhWEZ3vk8jTwMXyj5GKpdR2ayI0FpkO9 fiow== X-Gm-Message-State: APjAAAXadli3HZaaH9djSdELpvlFjW67Fxvtgnan5bF5NYVfn6lfehf0 +uDijTiLK/XO4AfiDcpU3XZrkbgkK9c= X-Received: by 2002:aa7:8289:: with SMTP id s9mr30827176pfm.208.1553814292676; Thu, 28 Mar 2019 16:04:52 -0700 (PDT) Received: from cloudburst.ASUS (cpe-66-75-72-255.hawaii.res.rr.com. [66.75.72.255]) by smtp.gmail.com with ESMTPSA id f1sm280911pgl.35.2019.03.28.16.04.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Mar 2019 16:04:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2019 13:03:55 -1000 Message-Id: <20190328230404.12909-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190328230404.12909-1-richard.henderson@linaro.org> References: <20190328230404.12909-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH for-4.1 v2 27/36] target/unicore32: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/unicore32/cpu.h | 5 ----- hw/unicore32/puv3.c | 2 +- target/unicore32/helper.c | 8 ++------ target/unicore32/op_helper.c | 2 +- target/unicore32/softmmu.c | 11 ++++------- target/unicore32/translate.c | 26 ++------------------------ target/unicore32/ucf64_helper.c | 2 +- 7 files changed, 11 insertions(+), 45 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 162e33257d..14c2d047fd 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -76,11 +76,6 @@ struct UniCore32CPU { CPUUniCore32State env; }; -static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env) -{ - return container_of(env, UniCore32CPU, env); -} - #define ENV_OFFSET offsetof(UniCore32CPU, env) void uc32_cpu_do_interrupt(CPUState *cpu); diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c index b42e600f74..132e6086ee 100644 --- a/hw/unicore32/puv3.c +++ b/hw/unicore32/puv3.c @@ -56,7 +56,7 @@ static void puv3_soc_init(CPUUniCore32State *env) /* Initialize interrupt controller */ cpu_intc = qemu_allocate_irq(puv3_intc_cpu_handler, - uc32_env_get_cpu(env), 0); + env_archcpu(env), 0); dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc); for (i = 0; i < PUV3_IRQS_NR; i++) { irqs[i] = qdev_get_gpio_in(dev, i); diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c index a5ff2ddb74..19ba865482 100644 --- a/target/unicore32/helper.c +++ b/target/unicore32/helper.c @@ -31,8 +31,6 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, uint32_t cop) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - /* * movc pp.nn, rn, #imm9 * rn: UCOP_REG_D @@ -101,7 +99,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, case 6: if ((cop <= 6) && (cop >= 2)) { /* invalid all tlb */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); return; } break; @@ -218,10 +216,8 @@ void helper_cp1_putc(target_ulong x) #ifdef CONFIG_USER_ONLY void switch_mode(CPUUniCore32State *env, int mode) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - if (mode != ASR_MODE_USER) { - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); + cpu_abort(env_cpu(env), "Tried to switch out of user mode\n"); } } diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c index e0a15882d3..44ff84420e 100644 --- a/target/unicore32/op_helper.c +++ b/target/unicore32/op_helper.c @@ -19,7 +19,7 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t excp) { - CPUState *cs = CPU(uc32_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = excp; cpu_loop_exit(cs); diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c index 00c7e0d028..2f31592faf 100644 --- a/target/unicore32/softmmu.c +++ b/target/unicore32/softmmu.c @@ -36,8 +36,6 @@ /* Map CPU modes onto saved register banks. */ static inline int bank_number(CPUUniCore32State *env, int mode) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - switch (mode) { case ASR_MODE_USER: case ASR_MODE_SUSR: @@ -51,7 +49,7 @@ static inline int bank_number(CPUUniCore32State *env, int mode) case ASR_MODE_INTR: return 4; } - cpu_abort(CPU(cpu), "Bad mode %x\n", mode); + cpu_abort(env_cpu(env), "Bad mode %x\n", mode); return -1; } @@ -126,8 +124,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address, int access_type, int is_user, uint32_t *phys_ptr, int *prot, target_ulong *page_size) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); int code; uint32_t table; uint32_t desc; @@ -174,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address, *page_size = TARGET_PAGE_SIZE; break; default: - cpu_abort(CPU(cpu), "wrong page type!"); + cpu_abort(cs, "wrong page type!"); } break; default: - cpu_abort(CPU(cpu), "wrong page type!"); + cpu_abort(cs, "wrong page type!"); } *phys_ptr = phys_addr; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 002569ff3b..2e8341d13b 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -179,7 +179,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) #define UCOP_SET_L UCOP_SET(24) #define UCOP_SET_S UCOP_SET(24) -#define ILLEGAL cpu_abort(CPU(cpu), \ +#define ILLEGAL cpu_abort(env_cpu(env), \ "Illegal UniCore32 instruction %x at line %d!", \ insn, __LINE__) @@ -187,7 +187,6 @@ static void store_reg(DisasContext *s, int reg, TCGv var) static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp, tmp2, tmp3; if ((insn & 0xfe000000) == 0xe0000000) { tmp2 = new_tmp(); @@ -213,7 +212,6 @@ static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; if ((insn & 0xff003fff) == 0xe1000400) { @@ -681,7 +679,6 @@ static inline long ucf64_reg_offset(int reg) /* UniCore-F64 single load/store I_offset */ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); int offset; TCGv tmp; TCGv addr; @@ -728,7 +725,6 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t in /* UniCore-F64 load/store multiple words */ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int i; int j, n, freg; TCGv tmp; @@ -814,7 +810,6 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in /* UniCore-F64 mrc/mcr */ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; if ((insn & 0xfe0003ff) == 0xe2000000) { @@ -879,8 +874,6 @@ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t ins /* UniCore-F64 convert instructions */ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - if (UCOP_UCF64_FMT == 3) { ILLEGAL; } @@ -947,8 +940,6 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn /* UniCore-F64 compare instructions */ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - if (UCOP_SET(25)) { ILLEGAL; } @@ -1027,8 +1018,6 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn /* UniCore-F64 data processing */ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - if (UCOP_UCF64_FMT == 3) { ILLEGAL; } @@ -1062,8 +1051,6 @@ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins /* Disassemble an F64 instruction */ static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - if (!UCOP_SET(29)) { if (UCOP_SET(26)) { do_ucf64_ldst_m(env, s, insn); @@ -1161,8 +1148,6 @@ static void gen_exception_return(DisasContext *s, TCGv pc) static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - switch (UCOP_CPNUM) { #ifndef CONFIG_USER_ONLY case 0: @@ -1177,14 +1162,13 @@ static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, break; default: /* Unknown coprocessor. */ - cpu_abort(CPU(cpu), "Unknown coprocessor!"); + cpu_abort(env_cpu(env), "Unknown coprocessor!"); } } /* data processing instructions */ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; TCGv tmp2; int logic_cc; @@ -1418,7 +1402,6 @@ static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* miscellaneous instructions */ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val; TCGv tmp; @@ -1544,7 +1527,6 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* SWP instruction */ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv addr; TCGv tmp; TCGv tmp2; @@ -1572,7 +1554,6 @@ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store hw/sb */ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv addr; TCGv tmp; @@ -1625,7 +1606,6 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store multiple words */ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val, i, mmu_idx; int j, n, reg, user, loaded_base; TCGv tmp; @@ -1767,7 +1747,6 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* branch (and link) */ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val; int32_t offset; TCGv tmp; @@ -1797,7 +1776,6 @@ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int insn; insn = cpu_ldl_code(env, s->pc); diff --git a/target/unicore32/ucf64_helper.c b/target/unicore32/ucf64_helper.c index fad3fa6618..e078e84437 100644 --- a/target/unicore32/ucf64_helper.c +++ b/target/unicore32/ucf64_helper.c @@ -78,7 +78,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits) void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); + UniCore32CPU *cpu = env_archcpu(env); int i; uint32_t changed;