From patchwork Sat Mar 23 19:09:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 160980 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2193190jan; Sat, 23 Mar 2019 12:40:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqyKdWbhkW3hOSceRXU3JALF8BWvBj5jtZw7XJsmAdNyiWuTUJuLEYl228evgREnF6V6vBUJ X-Received: by 2002:a0d:e705:: with SMTP id q5mr13893179ywe.238.1553370037723; Sat, 23 Mar 2019 12:40:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553370037; cv=none; d=google.com; s=arc-20160816; b=L4xB4tUWJXUya+9hVRVBKEot9Wi2g0zo/6GwMfZb9UFibPb7S5QCkVZBk5oYcDoEY4 1eB0hqyvlVObV3MlFdoaYStjcTwmS1HWAjZSEFq7AoSSSOj3mGtqN7Bd+U0VygfJ5Kjr aNRODcokqWibZTLhE4Z1Ja1PfbXaqZPcX/g2xLeAC/1Zxu93z/091pknDrO5anBAJQ+/ w3lJ0KxCBnLwHdbYY9cKdUDrtP0qcFo9tWejOa3sxgxxLVKrkN+eIqircrtOLC06JfO6 YdrQ1FgO7joUy7quQjHz8Xe87ViwNKH6ZNXKJyxp+1FJzqsBGHdKq8r4pxsKWR5vkK8T X32w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=M9STtJqpi+ezQozx9D8Bkma96uE2ten3P0bvZ8Hz2xM=; b=LZTg+n/0V1MkiPtYeqvDgrfKfZdExDcMIS270mPPOMR5cNE/MG98YRavtKzBmZePp4 B9SFbDO4gkA34su9/pekklTbIgJHP3QBgzCrSgbg6LaGg81x6mUShwA8gxG+1aFcCC7u SbcT4gZ5qiUhY9MiI+qBOmmtSlPfBximuw3ymfTdnz6bnrg7DzANiBq+pes1Nj/UDuHj nj+vuoOn+tSunQMKki/U5rSSEEAKYFH3zxz7U4fn9A/OU7D1kGpgET2QQ7FUi2V7nnDi NM/l+H9m3znkrjnTTetapY7ZhXL7rk2yEr7itys60kjxrl1sB0HNOFFYC81j0dsmj96Z zK6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nTFD9Orv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c6si6911196ybs.356.2019.03.23.12.40.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 23 Mar 2019 12:40:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nTFD9Orv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:47183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7mVR-0005Kh-4p for patch@linaro.org; Sat, 23 Mar 2019 15:40:37 -0400 Received: from eggs.gnu.org ([209.51.188.92]:50919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7mG0-0007mr-A5 for qemu-devel@nongnu.org; Sat, 23 Mar 2019 15:24:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h7m1r-00074l-HS for qemu-devel@nongnu.org; Sat, 23 Mar 2019 15:10:05 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:37524) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h7m1q-0006xd-M3 for qemu-devel@nongnu.org; Sat, 23 Mar 2019 15:10:03 -0400 Received: by mail-pf1-x441.google.com with SMTP id 8so3685321pfr.4 for ; Sat, 23 Mar 2019 12:09:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=M9STtJqpi+ezQozx9D8Bkma96uE2ten3P0bvZ8Hz2xM=; b=nTFD9OrvbEaiZb2qHqXwsRdzb7tVcLxteEPRHQP1ZY1EYiMZJDD2JQbb23r/mN/mpC XOYRGT9/ZN05qTHbJZhFqhgcpAYQMhybvSYNZkKyWqVZ7vEnVFaf/ULRw2tZsCa23Vr7 B+Awq5L6cYO6pZ/HtCDMUM2dRFhdpMuHYFWjgcs8dYuvQDupaNoQsI34oYn3u4hIm7tS d/rQjeWcsSNV16C9sJg/zA7PSCDEG9L8MWOIZ2vtKg5IbLxuA/Iofuid4MkHgMXFy2aZ s5slkTvRBlBD8QsIgVbLsIdTAXx/xbETM2sgFzwbeMmnbeFV1sxQupkmfrwgLIgkKMdO pybw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=M9STtJqpi+ezQozx9D8Bkma96uE2ten3P0bvZ8Hz2xM=; b=awsH6yqvV7NGctrIVoprrcS+Mqc1XibK3zLdgvTJzbnxx76MEmbTYOtueQeHj5EkHd tR66yiXcxJlqg79WMPUqtbuTfxIDhM0JnXvH4/P6hf8OV0LGTZO5iZg4YprJILf+MUmU nnlYtxdxQYLNCmxu9zQjR3KLyKyr9OUfsPAfCqciMTsKENcHVqymO73wBtz7waP+hEqx OlnPnJoi7fw4tuhRrYKxJ6oWxoOyYnX2wFlYGBK1fkjjQLQXqSiIPYagIy1CXIizIx94 IwXREeJNPqESSTV8tfU557DUyJ7N7OSbo3iu++aN0GYja5WzAGEJjdToKN5NLJyxvnCL LK2Q== X-Gm-Message-State: APjAAAVmjjFww6OzxoyIndkdqiBHggz29FoIkfFWqlINjqRGDrh9ve8d VO+SW7Ac3oiAbpkwKMqlhMI+N+XsD5w= X-Received: by 2002:a17:902:8a84:: with SMTP id p4mr16088205plo.2.1553368194217; Sat, 23 Mar 2019 12:09:54 -0700 (PDT) Received: from localhost.localdomain (174-21-5-201.tukw.qwest.net. [174.21.5.201]) by smtp.gmail.com with ESMTPSA id h184sm25990703pfc.78.2019.03.23.12.09.53 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Mar 2019 12:09:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 23 Mar 2019 12:09:11 -0700 Message-Id: <20190323190925.21324-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190323190925.21324-1-richard.henderson@linaro.org> References: <20190323190925.21324-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 21/35] target/riscv: Use env_cpu, env_archcpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 5 ----- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu_helper.c | 4 ++-- target/riscv/csr.c | 12 ++++++------ target/riscv/op_helper.c | 8 ++++---- 5 files changed, 13 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e97f6c4889..c18dd5eb24 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -211,11 +211,6 @@ typedef struct RISCVCPU { CPURISCVState env; } RISCVCPU; -static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) -{ - return container_of(env, RISCVCPU, env); -} - static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { return (env->misa & ext) != 0; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 31700f75d0..c1134597fd 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -25,7 +25,7 @@ void cpu_loop(CPURISCVState *env) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr, signum, sigcode; target_ulong sigaddr; target_ulong ret; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b17f169681..72f82c1ccf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -191,7 +191,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } } - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int va_bits = PGSHIFT + levels * ptidxbits; target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; @@ -320,7 +320,7 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int page_fault_exceptions = (env->priv_ver >= PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e1d91b6c60..97a4e10e3e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) if (env->priv_ver <= PRIV_VERSION_1_09_1) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) if (env->priv_ver >= PRIV_VERSION_1_10_0) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val) /* flush translation cache */ if (val != env->misa) { - tb_flush(CPU(riscv_env_get_cpu(env))); + tb_flush(env_cpu(env)); } env->misa = val; @@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu = riscv_env_get_cpu(env); + RISCVCPU *cpu = env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardware */ target_ulong mask = write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; @@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) return 0; } if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->sptbr = val & (((target_ulong) 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); } @@ -723,7 +723,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { return -1; } else { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->satp = val; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index b7dc18a41e..f078bafbe6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,7 +28,7 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index = exception; cpu_loop_exit_restore(cs, pc); @@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) void helper_wfi(CPURISCVState *env) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if (env->priv == PRV_S && env->priv_ver >= PRIV_VERSION_1_10_0 && @@ -143,8 +143,8 @@ void helper_wfi(CPURISCVState *env) void helper_tlb_flush(CPURISCVState *env) { - RISCVCPU *cpu = riscv_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); + if (env->priv == PRV_S && env->priv_ver >= PRIV_VERSION_1_10_0 && get_field(env->mstatus, MSTATUS_TVM)) {