From patchwork Sun Mar 17 09:08:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 160461 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp1405927jad; Sun, 17 Mar 2019 02:11:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqzWfSl22dKRVUc94usuDJe+hHfWo+AcmGXFuyfa3YFl5NJ6LZsA+P7QrgESfwJZ+ADVCqIv X-Received: by 2002:adf:f0c4:: with SMTP id x4mr7862849wro.37.1552813912139; Sun, 17 Mar 2019 02:11:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552813912; cv=none; d=google.com; s=arc-20160816; b=qbdMe4PpCqiEJVecFV4QK6syVoLmPqv/Pim5if2ZjBslUCc//m6tSb4eb7okJUfLHZ ePqp+UPYr/rLdgH1qy0uRr8gis0wF98t8c1vT4mWCZQiVvyRuO7yyRxYy3BDi4e45nCh kmkPeFa/Laan1Wid9oabXcHfSMyzOAAEL93V69k2SClGD/0Kj/7IV5eGaXUC++GdPUiq R7Eonp08rIUJRGaVk4ZVK6N2f5C+vJelVU+VO/CPz3+Gj+og8qm+rKI9eB5bij5Y9dcy Wg3IzZNq4uYHrIQkrFM8mYl+iWBRT6LPmzir2vVmyAUaW7elPHXtT+QCVPUdzCLTpW0I UkmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=+YKY+LXp9zIw9Md5dKypZwukvaZ0fElP7+gnW7iZQI0=; b=EBhAW8cKSRNYqlslx3szf7OHbFQQOtV10cXodMrpQ/CU033eCaLiTIdoXsv/iMJJ4W laX2/IJuNBl0oETUcVxv+5yuFFwDNGF0lpuDE5uGnXWvGIUJG6BGBxY38WhmBz4FMN7i SD945Ph7dnnleGrwo8ddVGL1DUI4PdHZbIFKfLAHFxtIGgbAizY0XmzUfyk+/mswDFyr tEpgkBVYmNj+ZCnmvLluUv3p7+c/iofE+4xmp9gb4S9k4Etu26gFpq8mGRwiIyEClJ6n 63IHW9m3E8JvB6g2a84SreN8wXcQurHfbbIsMpt3i0vSUzZJAuvjxrHhnOzW/L8B5zhi v6NA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eHrxIYYC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t14si3700456wri.124.2019.03.17.02.11.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 17 Mar 2019 02:11:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eHrxIYYC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:52125 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rpf-0008Om-0X for patch@linaro.org; Sun, 17 Mar 2019 05:11:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47714) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h5Rmk-0005er-EH for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h5Rmi-0004Af-OZ for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:50 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:32934) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h5Rmi-0004AJ-6O for qemu-devel@nongnu.org; Sun, 17 Mar 2019 05:08:48 -0400 Received: by mail-pg1-x543.google.com with SMTP id i7so6118063pgq.0 for ; Sun, 17 Mar 2019 02:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+YKY+LXp9zIw9Md5dKypZwukvaZ0fElP7+gnW7iZQI0=; b=eHrxIYYC/vKGI1Vd6HDkfM0oygGjyDrXnwaDD/9W6YSa9IqiZ2y2Qw96fvW2zC+Z+7 GrJWykvNygQ13GIUbPb426P3RZsOAZb6jWaVgIoqKNfcL7fXFwQUMlVSNUi/StnIa12G K88eKZ8u6bRkN7H8wVG4ubi4AXbwILGr//yPi7ok6WUAbDb/LNaA7oq+Jm/YTwKUaI8c QSenqWBJn2vI0ZJFr1rEDzvAH/2mGYerUrkIl7dfRZ2ih+uCKS8CCx+IMakcZ9bY9oSW IONK3lBezTcmVi3NivnFIimaJkLWStmKvS2B80Ave71BcTAvFdNmBNNHZMZP5ei6AUWQ t2vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+YKY+LXp9zIw9Md5dKypZwukvaZ0fElP7+gnW7iZQI0=; b=BQ0YTKM8vYkPgpJiEPM9Dl6T5mfQ0VVAzoSELJbKaq3DXf6oPIs/TSivGGJ82HNX7s D+FoON5tG8eafO0lPWh00nmzl3OXtYruQZfVD75NiqhTXqqMKokzOxyiQwoGjYbu2yuu kbClwjKvNEi9ft94GswHyNWqlig1/1c7y8T7nIyYTgUe1AhLMLaGiCRpBEYXKK9U7J4I q0meXKC+O1irP9f08OP1hDK4RzFC+nVnxLusJ6n6fL5PdtjPcDAeIS4FjPb2TkD6Hn9I Iit0jxLRQvluOIgF5Tj/zDhbLO6+11eaq7Obeb/bQxM3/8gBReZLE8h+GjIg3wvcfV6L hPng== X-Gm-Message-State: APjAAAW/GaDK+XnqzTevxbgzfbvgOfzhkIQdlBS6dTpQttkhTyGIwLY2 VsJv+vT+qOQ540w6htBsIbug2oV37hQ= X-Received: by 2002:a63:da43:: with SMTP id l3mr12306395pgj.164.1552813726763; Sun, 17 Mar 2019 02:08:46 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id b85sm19378435pfj.56.2019.03.17.02.08.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Mar 2019 02:08:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Mar 2019 02:08:28 -0700 Message-Id: <20190317090834.5552-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190317090834.5552-1-richard.henderson@linaro.org> References: <20190317090834.5552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH for-4.1 v2 07/13] tcg: Add INDEX_op_dup_mem_vec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow the backend to expand dup from memory directly, instead of forcing the value into a temp first. This is especially important if integer/vector register moves do not exist. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/tcg-op.h | 1 + tcg/tcg-opc.h | 1 + tcg/tcg.h | 1 + tcg/tcg-op-gvec.c | 88 +++++++++++++++++++++------------------- tcg/tcg-op-vec.c | 11 +++++ tcg/tcg.c | 2 + 9 files changed, 66 insertions(+), 41 deletions(-) -- 2.17.2 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 2d93cf404e..8ce99fc9c8 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -137,6 +137,7 @@ typedef enum { #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_dupm_vec 0 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7995fe3eab..8e8d59f4f4 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -187,6 +187,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_dupm_vec 0 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 683eb807ae..5143ee853a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -152,6 +152,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 +#define TCG_TARGET_HAS_dupm_vec 0 void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index d3e51b15af..64cd3f58ef 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -950,6 +950,7 @@ void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 4e0238ad1a..b8ad147377 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -211,6 +211,7 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) +DEF(dupm_vec, 1, 1, 1, TCG_OPF_VECTOR | IMPL(TCG_TARGET_HAS_dupm_vec)) DEF(dup_vec, 1, 1, 0, IMPLVEC) DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) diff --git a/tcg/tcg.h b/tcg/tcg.h index 32b7cf3489..f7c12de75a 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -185,6 +185,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_mul_vec 0 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_dupm_vec 0 #else #define TCG_TARGET_MAYBE_vec 1 #endif diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 0996ef0812..59ab516bf0 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -390,6 +390,40 @@ static TCGType choose_vector_type(TCGOpcode op, unsigned vece, uint32_t size, return 0; } +static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz, + uint32_t maxsz, TCGv_vec t_vec) +{ + uint32_t i = 0; + + switch (type) { + case TCG_TYPE_V256: + /* Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size == 80 would be expanded with 2x32 + 1x16. + */ + for (; i + 32 <= oprsz; i += 32) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); + } + /* fallthru */ + case TCG_TYPE_V128: + for (; i + 16 <= oprsz; i += 16) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); + } + break; + case TCG_TYPE_V64: + for (; i < oprsz; i += 8) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); + } + break; + default: + g_assert_not_reached(); + } + + if (oprsz < maxsz) { + expand_clr(dofs + oprsz, maxsz - oprsz); + } +} + /* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C. * Only one of IN_32 or IN_64 may be set; * IN_C is used if IN_32 and IN_64 are unset. @@ -429,49 +463,11 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, } else if (in_64) { tcg_gen_dup_i64_vec(vece, t_vec, in_64); } else { - switch (vece) { - case MO_8: - tcg_gen_dup8i_vec(t_vec, in_c); - break; - case MO_16: - tcg_gen_dup16i_vec(t_vec, in_c); - break; - case MO_32: - tcg_gen_dup32i_vec(t_vec, in_c); - break; - default: - tcg_gen_dup64i_vec(t_vec, in_c); - break; - } + tcg_gen_dupi_vec(vece, t_vec, in_c); } - - i = 0; - switch (type) { - case TCG_TYPE_V256: - /* Recall that ARM SVE allows vector sizes that are not a - * power of 2, but always a multiple of 16. The intent is - * that e.g. size == 80 would be expanded with 2x32 + 1x16. - */ - for (; i + 32 <= oprsz; i += 32) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); - } - /* fallthru */ - case TCG_TYPE_V128: - for (; i + 16 <= oprsz; i += 16) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); - } - break; - case TCG_TYPE_V64: - for (; i < oprsz; i += 8) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); - } - break; - default: - g_assert_not_reached(); - } - + do_dup_store(type, dofs, oprsz, maxsz, t_vec); tcg_temp_free_vec(t_vec); - goto done; + return; } /* Otherwise, inline with an integer type, unless "large". */ @@ -1287,6 +1283,16 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz, void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz) { + if (TCG_TARGET_HAS_dupm_vec) { + TCGType type = choose_vector_type(INDEX_op_dupm_vec, vece, oprsz, 0); + if (type != 0) { + TCGv_vec t_vec = tcg_temp_new_vec(type); + tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); + do_dup_store(type, dofs, oprsz, maxsz, t_vec); + tcg_temp_free_vec(t_vec); + return; + } + } if (vece <= MO_32) { TCGv_i32 in = tcg_temp_new_i32(); switch (vece) { diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index cfb18682b1..ce7987b858 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -194,6 +194,17 @@ void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TCGv_i32 a) vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); } +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec r, TCGv_ptr b, + tcg_target_long ofs) +{ + TCGArg ri = tcgv_vec_arg(r); + TCGArg bi = tcgv_ptr_arg(b); + TCGTemp *rt = arg_temp(ri); + TCGType type = rt->base_type; + + vec_gen_3(INDEX_op_dupm_vec, type, vece, ri, bi, ofs); +} + static void vec_gen_ldst(TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o) { TCGArg ri = tcgv_vec_arg(r); diff --git a/tcg/tcg.c b/tcg/tcg.c index b5389ea767..e0d771d610 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1623,6 +1623,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_smax_vec: case INDEX_op_umax_vec: return have_vec && TCG_TARGET_HAS_minmax_vec; + case INDEX_op_dupm_vec: + return have_vec && TCG_TARGET_HAS_dupm_vec; default: tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);