[v4,15/22] target/arm: Clean address for DC ZVA

Message ID	20190307170440.3113-16-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Thu, 7 Mar 2019 09:04:33 -0800 Message-Id: <20190307170440.3113-16-richard.henderson@linaro.org> In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v4 15/22] target/arm: Clean address for DC ZVA Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	[v4,01/22] target/arm: Add MTE_ACTIVE to tb_flags \| expand [v4,01/22] target/arm: Add MTE_ACTIVE to tb_flags [v4,02/22] target/arm: Extract TCMA with ARMVAParameters [v4,03/22] target/arm: Add MTE system registers [v4,04/22] target/arm: Add helper_mte_check{1, 2} [v4,05/22] target/arm: Suppress tag check for sp+offset [v4,06/22] target/arm: Implement the IRG instruction [v4,07/22] target/arm: Implement ADDG, SUBG instructions [v4,08/22] target/arm: Implement the GMI instruction [v4,09/22] target/arm: Implement the SUBP instruction [v4,10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY [v4,11/22] target/arm: Implement LDG, STG, ST2G instructions [v4,12/22] target/arm: Implement the STGP instruction [v4,13/22] target/arm: Implement the LDGM and STGM instructions [v4,14/22] target/arm: Implement the access tag cache flushes [v4,15/22] target/arm: Clean address for DC ZVA [v4,16/22] target/arm: Implement data cache set allocation tags [v4,17/22] target/arm: Set PSTATE.TCO on exception entry [v4,18/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs [v4,19/22] target/arm: Create tagged ram when MTE is enabled [v4,20/22] target/arm: Create a TLB entry for tag physical address space [v4,21/22] target/arm: Add allocation tag storage for system mode [v4,22/22] target/arm: Enable MTE

Message ID

20190307170440.3113-16-richard.henderson@linaro.org

State

Superseded

Headers

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
	209.51.188.17 as permitted sender) client-ip=209.51.188.17; 
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu,  7 Mar 2019 09:04:33 -0800
Message-Id: <20190307170440.3113-16-richard.henderson@linaro.org>
In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org>
References: <20190307170440.3113-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH v4 15/22] target/arm: Clean address for DC ZVA
Precedence: list
Cc: peter.maydell@linaro.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

[v4,01/22] target/arm: Add MTE_ACTIVE to tb_flags | expand

Commit Message

Richard Henderson March 7, 2019, 5:04 p.m. UTC

This data access was forgotten in the previous patch.

Fixes: 3a471103ac1823ba
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.2

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e02d85f317..a02c829db2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1894,7 +1894,7 @@  static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         return;
     case ARM_CP_DC_ZVA:
         /* Writes clear the aligned block of memory which rt points into. */
-        tcg_rt = cpu_reg(s, rt);
+        tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false);
         gen_helper_dc_zva(cpu_env, tcg_rt);
         return;
     default:

[v4,15/22] target/arm: Clean address for DC ZVA

Commit Message

Patch