From patchwork Wed Feb 20 05:04:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158763 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4497507jaa; Tue, 19 Feb 2019 21:07:38 -0800 (PST) X-Google-Smtp-Source: AHgI3IYJVU78PkMSQWWUq/7LVe1g0B7T84IAlUhnDwRvkNOmBicmg7FQoKT+i8utZ9+TZl6NVfge X-Received: by 2002:a0d:dc07:: with SMTP id f7mr25140845ywe.440.1550639258267; Tue, 19 Feb 2019 21:07:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550639258; cv=none; d=google.com; s=arc-20160816; b=h0xYkZlwIMhmfEONNPmrg0xCb5AGxsgPsWAqdQMjpTuZs/RHR4S9a/jlMBCfCAELZe AZ3CoMv7CYaYgDXCmaN5eXjyR4wWdoz20ztLRaEntcVB0tCqywDve6UfZ7LktRlIEhTF Mu3aD8Ae39mq/6bRS+mob7lB2HJWnNRttr9CiDBX3KBRUEkAuW4h4lCgZood/JEJmEGG cHTVT/ouc32yu03XjAKw8EbedP8Z2IiHoPRceU/LVIOtMVWR4gpTLeTazC62ai+pfjkR tXVBHYKHH75X3f+CyiOesgnA6C5CCYEoxKbqSqZSEakDZJSSV+qAnac1CLtikNIEvjeq ilGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=FK3Xke/p+WsVbKom639alhUbyDxy/Xj7MbX2OQ5+/BI=; b=He7u1urWNfpzcJ8xb1OKBVSecmkUudjX2GRiKbma5AonUYZNdAlNHQpQZrkdjPE3BE sLoDhLgdV8pRSOX7WDxhA+kPfXGMU32NmvAA5eY0KFLi2Pqg5WUdVnIybvFc6vU/uTKB BXt5IloUfFGXioS506vRsAurt+CAnHQCAls+p0jPtDMOHhlYYlE9kN2UGOtmFpVVRbTd a2HBLckbVEc7OcJLK5gKp38H5KBru4aS5YoLFWYTz1WEiZdp2xCqpzLFTayxtwWkJdpz 2xnDw1GZihXmTjcDjvzSauDJ9Meg57skzqC4pedTpclzyVBMRM2pTW07+XS/+KdRPrQU pD0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bJU+lWz8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 198si10407474ywe.191.2019.02.19.21.07.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 19 Feb 2019 21:07:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bJU+lWz8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:33985 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwK6b-0004oZ-Nj for patch@linaro.org; Wed, 20 Feb 2019 00:07:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43782) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwK44-0003tM-QQ for qemu-devel@nongnu.org; Wed, 20 Feb 2019 00:05:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gwK43-0004y1-9Q for qemu-devel@nongnu.org; Wed, 20 Feb 2019 00:05:00 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:41074) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gwK42-0004x7-UD for qemu-devel@nongnu.org; Wed, 20 Feb 2019 00:04:59 -0500 Received: by mail-pg1-x544.google.com with SMTP id m1so11228768pgq.8 for ; Tue, 19 Feb 2019 21:04:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FK3Xke/p+WsVbKom639alhUbyDxy/Xj7MbX2OQ5+/BI=; b=bJU+lWz8aSInMCLLk4tqvZYyrTMX9xBNB+gvOK17+iGQDd/3yW5Mjl9cPujz6bvIxO nX35sYc3GNJ3fX3clPWjd3XbgbX+yymTXMgNLlvCc3sq7jkKgJ+wPRJNr9jNNlfoAF13 cuRadZIpbYeorsyLatf6z6kVOoeJFL7+Zo8voSlZMn6Uw7ik5LlqhP0+YjMk7ZeGPvS/ D/puDDQ9UshxKtTILRLfedWLVvHQ/jkUBIBiGRB5hJ4XSpWl+uwUo6QyND8XJov2uKkk LtXNWaKDXzDxe8tAvni1HOoD0makTyxMdsbx4akHBMJeywnpA/t5QdC68lTj6e9+X9Vk KgbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FK3Xke/p+WsVbKom639alhUbyDxy/Xj7MbX2OQ5+/BI=; b=QkWQeDhMNz6vhvJ732Jisitt1pocMRu+WC0Sb3hs9NZo0ERPUqOI4jplf4Jb4vjrdt AKFGST7bOC74iwHqJCppymDswP32k4S2BAXo1NE53C3c0BLpZ5ZP0tLwmk9RD5jWzAU4 uIT3FadKhWWWjtUBfzTb/JNJHxmHYis0laPNK0u2H7C6/WZgb0REMquMtcSPLP9DITMJ n0XQFERt6H8SifNMnaMYFQg3Gm6lhxNnp4BilXbBjAaW2ao56aRXqEui2ps2msq+h+CO z1FWRELp91TZE78Zd6/cZfmgCENUDqc0qsc4ctd+FDzAsJbwEnhiwNO1DOp7BiYrWDRD 1r3g== X-Gm-Message-State: AHQUAuZGBNilbT+Fr+yQ7hNsYwt663w7pHJ/OU6X1VkIgkNyjTwWfLKf mPRfACN778aDqNYQmb4S3gZr0pYAx6A= X-Received: by 2002:a65:6099:: with SMTP id t25mr31073160pgu.448.1550639096704; Tue, 19 Feb 2019 21:04:56 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id w10sm25228143pge.8.2019.02.19.21.04.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Feb 2019 21:04:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 21:04:50 -0800 Message-Id: <20190220050451.10939-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190220050451.10939-1-richard.henderson@linaro.org> References: <20190220050451.10939-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 2/3] target/arm: Implement ARMv8.4-CondM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 97 +++++++++++++++++++++++++++++++++++++- 4 files changed, 103 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f8ff795dcf..000e778619 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3375,6 +3375,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; } +static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; +} + static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 3a50d587ff..ef7138839d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -602,6 +602,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); + GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); #undef GET_FEATURE_ID diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7bd761b8f5..27b95ef787 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -334,6 +334,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1); cpu->isar.id_aa64isar0 = t; t = cpu->isar.id_aa64isar1; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0e16487be0..b88eccef53 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1655,6 +1655,14 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_TOO_MANY; switch (op) { + case 0x00: /* CFINV */ + if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) { + goto do_unallocated; + } + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); + s->base.is_jmp = DISAS_NEXT; + break; + case 0x05: /* SPSel */ if (s->current_el == 0) { goto do_unallocated; @@ -1719,7 +1727,6 @@ static void gen_get_nzcv(TCGv_i64 tcg_rt) } static void gen_set_nzcv(TCGv_i64 tcg_rt) - { TCGv_i32 nzcv = tcg_temp_new_i32(); @@ -4729,6 +4736,82 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn) } } +/* Rotate right into flags + * 31 30 29 21 15 10 5 4 0 + * +--+--+--+-----------------+--------+-----------+------+--+------+ + * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask | + * +--+--+--+-----------------+--------+-----------+------+--+------+ + */ +static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn) +{ + int mask = extract32(insn, 0, 4); + int o2 = extract32(insn, 4, 1); + int rn = extract32(insn, 5, 5); + int imm6 = extract32(insn, 15, 6); + int sf_op_s = extract32(insn, 29, 3); + TCGv_i64 tcg_rn; + TCGv_i32 nzcv; + + if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) { + unallocated_encoding(s); + return; + } + + tcg_rn = read_cpu_reg(s, rn, 1); + tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6); + + nzcv = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(nzcv, tcg_rn); + + if (mask & 8) { /* N */ + tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3); + } + if (mask & 4) { /* Z */ + tcg_gen_not_i32(cpu_ZF, nzcv); + tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); + } + if (mask & 2) { /* C */ + tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1); + } + if (mask & 1) { /* V */ + tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); + } + + tcg_temp_free_i32(nzcv); +} + +/* Evaluate into flags + * 31 30 29 21 15 14 10 5 4 0 + * +--+--+--+-----------------+---------+----+---------+------+--+------+ + * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | + * +--+--+--+-----------------+---------+----+---------+------+--+------+ + */ +static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) +{ + int o3_mask = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + int o2 = extract32(insn, 15, 6); + int sz = extract32(insn, 14, 1); + int sf_op_s = extract32(insn, 29, 3); + TCGv_i32 tmp; + int shift; + + if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd || + !dc_isar_feature(aa64_condm_4, s)) { + unallocated_encoding(s); + return; + } + shift = sz ? 16 : 24; /* SETF16 or SETF8 */ + + tmp = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); + tcg_gen_shli_i32(cpu_NF, tmp, shift); + tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); + tcg_gen_mov_i32(cpu_ZF, cpu_NF); + tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); + tcg_temp_free_i32(tmp); +} + /* Conditional compare (immediate / register) * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ @@ -5428,6 +5511,18 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) disas_adc_sbc(s, insn); break; + case 0x01: /* Rotate right into flags */ + case 0x21: + disas_rotate_right_into_flags(s, insn); + break; + + case 0x02: /* Evaluate into flags */ + case 0x12: + case 0x22: + case 0x32: + disas_evaluate_into_flags(s, insn); + break; + default: goto do_unallocated; }