From patchwork Fri Feb 15 19:23:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158543 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1065636jaa; Fri, 15 Feb 2019 11:29:29 -0800 (PST) X-Google-Smtp-Source: AHgI3IapMmpb7dE4eYG2j1KtfuJwowubujPxzdYY/dAJz/j65EnBlz75grMd2Uqq2etbMNB0PSay X-Received: by 2002:a0d:dc07:: with SMTP id f7mr8910632ywe.440.1550258969220; Fri, 15 Feb 2019 11:29:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550258969; cv=none; d=google.com; s=arc-20160816; b=hEhfcbmwRfOdd1eUikUMKp1HizI7VgYcyDesSjZ/7vBJYEzrb5s+PckBpbWG+zQW0r q/Q2SiGK6Na0bTEpEvO6/P1sonONI0zUa2SGJMfkWhHDF3Uxc7TGOVrplHxWQlK81fwc zFHM4y2t2msrHtFj2hi7ICJY7cNL2w90J0pQhQm5Y99E22UQIj9q+S9wG3gDFoGqNAdi JMzU0SjrgyEYF3PhALNdMyZE2H4MBmtijkkynLIigDAvAE7bNPl4829MbeN0HHMkAUOK xHqyDzWt2UklMcjrmOVxnkNS0jlst1X5GEf9yiMD9laRCVRMW/x9l4b++cZ2YwfgkwNQ Qu8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BU/ewC8+prSMkfZW9PvJmy7JChgMnIDyBTrL1xlJ2p4=; b=BD1RUVQ1dimHqQalD+JKLM3YLNRN+xO8Wi/jgTLEYgyo8bLy8SWb/ghPaKKIyvT2qa JVUiAzpkKNj1cC91vGM1rQqa0Y0DzhPL/5lQeAcd2KVozkswbMygoaOBxsuCeV8u5Ce3 CJmgFlvqUCZvVZ2sGkL9qa7ldXHXfkA0XAkvHgebNBrB+2n78zgnBl/71dSzwzxyXTdP atZUclMFpWL7xV959YBww/xI0AKX9VhTHsJbaIyfgLpoPc53T4pHFFxDcWq7CuwdobDM GEfsGsc/19k1tmCrRN38AG+Wgnkhn215ovshZOhiGKwxOEXyLxIp4x+QNWqs/oOVYz4u +0RA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V1l+BJ5g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t8si3698961yba.36.2019.02.15.11.29.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 15 Feb 2019 11:29:29 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V1l+BJ5g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:45104 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gujAu-0001IF-Od for patch@linaro.org; Fri, 15 Feb 2019 14:29:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33354) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guj4t-0005O9-4E for qemu-devel@nongnu.org; Fri, 15 Feb 2019 14:23:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guj4s-0003Is-90 for qemu-devel@nongnu.org; Fri, 15 Feb 2019 14:23:15 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:38534) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guj4s-0003GJ-2c for qemu-devel@nongnu.org; Fri, 15 Feb 2019 14:23:14 -0500 Received: by mail-pl1-x643.google.com with SMTP id e5so5410696plb.5 for ; Fri, 15 Feb 2019 11:23:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BU/ewC8+prSMkfZW9PvJmy7JChgMnIDyBTrL1xlJ2p4=; b=V1l+BJ5gpJMFk9bdScaDkEo7q/JbrcmHxoUoOp4vkFfsNuLA/QWCGoqM30RspchHyW G4fLG7Y3pGHTTGBIFj7jwo82nnRYW+x35lLFdP6/El1qY4Hm0oVMzlfTtOxEUXHvvs0Y TWX23ZOMhGcPIFlr25noBZPjTB+vw9KOOeXNR6VQQrXt4o4oyLcl2yOlBtnBLEB4FIBe P3BFs8NyJFvS+C45D0P0BtRTJydD8HC9c1ppGbMAQ6v75i5XJY/WE6YXIXqMzMDFsyYk RE8NdYlWmE9gUz9TaOh39Q83QEI0wtRJYRewy8E1gsQKNL75Rc36AffIW7VHmFP8Bx2G W5MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BU/ewC8+prSMkfZW9PvJmy7JChgMnIDyBTrL1xlJ2p4=; b=tUSm4dARZUJ9gQMtBBXA1rbSAhmr8jjgbaIHcspWok0E5pKtpwr7UKUqs+psTzb/r3 9dHhiNC1LDnC0XaaPxNyenP1ZArHmUnNGo/wjDVOqyrPIMlmBt4LVSYjR8EXmEJbF2Ys oa0nGv4yc6EXRBONFtFWbW2ifIGlKPi2m8MIUwL38q3mcoSSEG9lYxUV64XNSbB76pzV Hy1/KwKKT/Vx9HMfOPKgoEqUNfXkR0Moahy6sqwOFsJ0+p+SA2gopc+V9MohesZszi3H SrLl8Ei2/YLKxHy7X6/eGWZSyindLDHov4dgb6IrTeQQYof1MRpHYz92Z2rm9KfavdHd faKA== X-Gm-Message-State: AHQUAuaUi3ME9KOVsF2ACUmXuyIgjDhMQzCX1LAELGTczi5geGFqZhzi GzUkwmiaMi3cW5lC9G0LCpPzdkLWeXA= X-Received: by 2002:a17:902:34a:: with SMTP id 68mr11996183pld.268.1550258592691; Fri, 15 Feb 2019 11:23:12 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id o85sm15161596pfi.105.2019.02.15.11.23.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Feb 2019 11:23:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 15 Feb 2019 11:23:00 -0800 Message-Id: <20190215192302.27855-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190215192302.27855-1-richard.henderson@linaro.org> References: <20190215192302.27855-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 6/8] target/arm: Implement FMLAL and FMLSL for aarch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++++ target/arm/translate-a64.c | 50 +++++++++++++++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1eea1a408b..69589573e4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3356,6 +3356,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; } +static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c56e878787..9a4c561982 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10917,9 +10917,26 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn) if (!fp_access_check(s)) { return; } - handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); return; + + case 0x1d: /* FMLAL */ + case 0x3d: /* FMLSL */ + case 0x59: /* FMLAL2 */ + case 0x79: /* FMLSL2 */ + if (size & 1 || !dc_isar_feature(aa64_fhm, s)) { + unallocated_encoding(s); + return; + } + if (fp_access_check(s)) { + int is_s = extract32(insn, 23, 1); + int is_2 = extract32(insn, 29, 1); + int data = (is_2 << 1) | is_s; + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, data, + gen_helper_gvec_fmlal_h); + } + return; + default: unallocated_encoding(s); return; @@ -12739,6 +12756,17 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } is_fp = 2; break; + case 0x00: /* FMLAL */ + case 0x04: /* FMLSL */ + case 0x18: /* FMLAL2 */ + case 0x1c: /* FMLSL2 */ + if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) { + unallocated_encoding(s); + return; + } + size = MO_16; + is_fp = 3; + break; default: unallocated_encoding(s); return; @@ -12780,6 +12808,9 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } break; + case 3: /* other fp, size already set and verified. */ + break; + default: /* integer */ switch (size) { case MO_8: @@ -12849,6 +12880,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) tcg_temp_free_ptr(fpst); } return; + + case 0x00: /* FMLAL */ + case 0x04: /* FMLSL */ + case 0x18: /* FMLAL2 */ + case 0x1c: /* FMLSL2 */ + { + int is_s = extract32(opcode, 2, 1); + int is_2 = u; + int data = (index << 2) | (is_2 << 1) | is_s; + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), data, + gen_helper_gvec_fmlal_idx_h); + tcg_temp_free_ptr(fpst); + } + return; } if (size == 3) {