[v2,26/26] tests/tcg/aarch64: Add mte smoke tests

Message ID	20190211010829.29869-27-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:29 -0800 Message-Id: <20190211010829.29869-27-richard.henderson@linaro.org> In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 26/26] tests/tcg/aarch64: Add mte smoke tests Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Implement ARMv8.5-MemTag \| expand [v2,00/26] target/arm: Implement ARMv8.5-MemTag [v2,01/26] target/arm: Split out arm_sctlr [v2,02/26] target/arm: Split helper_msr_i_pstate into 3 [v2,03/26] target/arm: Add clear_pstate_bits, share gen_ss_advance [v2,04/26] target/arm: Add MTE_ACTIVE to tb_flags [v2,05/26] target/arm: Extract TCMA with ARMVAParameters [v2,06/26] target/arm: Add MTE system registers [v2,07/26] target/arm: Assert no manual change to CACHED_PSTATE_BITS [v2,08/26] target/arm: Fill in helper_mte_check [v2,09/26] target/arm: Suppress tag check for sp+offset [v2,10/26] target/arm: Implement the IRG instruction [v2,11/26] target/arm: Implement ADDG, SUBG instructions [v2,12/26] target/arm: Implement the GMI instruction [v2,13/26] target/arm: Implement the SUBP instruction [v2,14/26] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY [v2,15/26] target/arm: Implement LDG, STG, ST2G instructions [v2,16/26] target/arm: Implement the STGP instruction [v2,17/26] target/arm: Implement the access tag cache flushes [v2,18/26] target/arm: Implement data cache set allocation tags [v2,19/26] target/arm: Set PSTATE.TCO on exception entry [v2,20/26] tcg: Introduce target-specific page data for user-only [v2,21/26] target/arm: Cache the Tagged bit for a page in MemTxAttrs [v2,22/26] target/arm: Create tagged ram when MTE is enabled [v2,23/26] target/arm: Add allocation tag storage for user mode [v2,24/26] target/arm: Add allocation tag storage for system mode [v2,25/26] target/arm: Enable MTE [v2,26/26] tests/tcg/aarch64: Add mte smoke tests

Message ID

20190211010829.29869-27-richard.henderson@linaro.org

State

Superseded

Headers

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Sun, 10 Feb 2019 17:08:29 -0800
Message-Id: <20190211010829.29869-27-richard.henderson@linaro.org>
In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org>
References: <20190211010829.29869-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH v2 26/26] tests/tcg/aarch64: Add mte smoke tests
Precedence: list
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Implement ARMv8.5-MemTag | expand

Commit Message

Richard Henderson Feb. 11, 2019, 1:08 a.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tests/tcg/aarch64/mte-1.c         | 27 +++++++++++++++++++++
 tests/tcg/aarch64/mte-2.c         | 39 +++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |  4 ++++
 3 files changed, 70 insertions(+)
 create mode 100644 tests/tcg/aarch64/mte-1.c
 create mode 100644 tests/tcg/aarch64/mte-2.c

-- 
2.17.2

diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c
new file mode 100644
index 0000000000..740bf506f1
--- /dev/null
+++ b/tests/tcg/aarch64/mte-1.c
@@ -0,0 +1,27 @@ 
+/*
+ * Memory tagging, basic pass cases.
+ */
+
+#include <assert.h>
+
+asm(".arch armv8.5-a+memtag");
+
+int data[16 / sizeof(int)] __attribute__((aligned(16)));
+
+int main(int ac, char **av)
+{
+    int *p0 = data;
+    int *p1, *p2;
+    long c;
+
+    asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1));
+    assert(p1 != p0);
+    asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1));
+    assert(c == 0);
+
+    asm("stg [%0]" : : "r"(p1));
+    asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0));
+    assert(p1 == p2);
+
+    return 0;
+}
diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c
new file mode 100644
index 0000000000..4d2004ab41
--- /dev/null
+++ b/tests/tcg/aarch64/mte-2.c
@@ -0,0 +1,39 @@ 
+/*
+ * Memory tagging, basic fail cases.
+ */
+
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+
+asm(".arch armv8.5-a+memtag");
+
+int data[16 / sizeof(int)] __attribute__((aligned(16)));
+
+void pass(int sig)
+{
+    exit(0);
+}
+
+int main(int ac, char **av)
+{
+    int *p0 = data;
+    int *p1, *p2;
+    long excl = 1;
+
+    /* Create two differently tagged pointers.  */
+    asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl));
+    asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1));
+    assert(excl != 1);
+    asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl));
+    assert(p1 != p2);
+
+    /* Store the tag from the first pointer.  */
+    asm("stg [%0]" : : "r"(p1));
+
+    *p1 = 0;
+    signal(SIGSEGV, pass);
+    *p2 = 0;
+
+    assert(0);
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 55420aeea6..614dfcd14d 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -22,4 +22,8 @@  AARCH64_TESTS += bti-1
 bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib
 run-bti-1: QEMU += -cpu max,x-guarded-pages=on
 
+AARCH64_TESTS += mte-1 mte-2
+mte-%: CFLAGS += -O -g
+run-mte-%: QEMU += -cpu max,x-tagged-pages=on
+
 TESTS:=$(AARCH64_TESTS)

[v2,26/26] tests/tcg/aarch64: Add mte smoke tests

Commit Message

Patch