@@ -10719,6 +10719,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
uint64_t descaddrmask;
bool aarch64 = arm_el_is_aa64(env, el);
bool guarded = false;
+ uint8_t memattr;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@@ -10949,17 +10950,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
txattrs->target_tlb_bit0 = true;
}
+ if (mmu_idx == ARMMMUIdx_S2NS) {
+ memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4));
+ } else {
+ /* Index into MAIR registers for cache attributes */
+ uint64_t mair = env->cp15.mair_el[el];
+ memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8);
+ }
+
+ /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB. */
+ if (aarch64 && memattr == 0xf0 && cpu_isar_feature(aa64_mte, cpu)) {
+ txattrs->target_tlb_bit1 = true;
+ }
+
if (cacheattrs != NULL) {
- if (mmu_idx == ARMMMUIdx_S2NS) {
- cacheattrs->attrs = convert_stage2_attrs(env,
- extract32(attrs, 0, 4));
- } else {
- /* Index into MAIR registers for cache attributes */
- uint8_t attrindx = extract32(attrs, 0, 3);
- uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
- assert(attrindx <= 7);
- cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
- }
+ cacheattrs->attrs = memattr;
cacheattrs->shareability = extract32(attrs, 6, 2);
}
This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.17.2