[v2,12/26] target/arm: Implement the GMI instruction

Message ID	20190211010829.29869-13-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:15 -0800 Message-Id: <20190211010829.29869-13-richard.henderson@linaro.org> In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 12/26] target/arm: Implement the GMI instruction Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Implement ARMv8.5-MemTag \| expand [v2,00/26] target/arm: Implement ARMv8.5-MemTag [v2,01/26] target/arm: Split out arm_sctlr [v2,02/26] target/arm: Split helper_msr_i_pstate into 3 [v2,03/26] target/arm: Add clear_pstate_bits, share gen_ss_advance [v2,04/26] target/arm: Add MTE_ACTIVE to tb_flags [v2,05/26] target/arm: Extract TCMA with ARMVAParameters [v2,06/26] target/arm: Add MTE system registers [v2,07/26] target/arm: Assert no manual change to CACHED_PSTATE_BITS [v2,08/26] target/arm: Fill in helper_mte_check [v2,09/26] target/arm: Suppress tag check for sp+offset [v2,10/26] target/arm: Implement the IRG instruction [v2,11/26] target/arm: Implement ADDG, SUBG instructions [v2,12/26] target/arm: Implement the GMI instruction [v2,13/26] target/arm: Implement the SUBP instruction [v2,14/26] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY [v2,15/26] target/arm: Implement LDG, STG, ST2G instructions [v2,16/26] target/arm: Implement the STGP instruction [v2,17/26] target/arm: Implement the access tag cache flushes [v2,18/26] target/arm: Implement data cache set allocation tags [v2,19/26] target/arm: Set PSTATE.TCO on exception entry [v2,20/26] tcg: Introduce target-specific page data for user-only [v2,21/26] target/arm: Cache the Tagged bit for a page in MemTxAttrs [v2,22/26] target/arm: Create tagged ram when MTE is enabled [v2,23/26] target/arm: Add allocation tag storage for user mode [v2,24/26] target/arm: Add allocation tag storage for system mode [v2,25/26] target/arm: Enable MTE [v2,26/26] tests/tcg/aarch64: Add mte smoke tests

Message ID

20190211010829.29869-13-richard.henderson@linaro.org

State

Superseded

Headers

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
	209.51.188.17 as permitted sender) client-ip=209.51.188.17; 
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Sun, 10 Feb 2019 17:08:15 -0800
Message-Id: <20190211010829.29869-13-richard.henderson@linaro.org>
In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org>
References: <20190211010829.29869-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH v2 12/26] target/arm: Implement the GMI
	instruction
Precedence: list
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Implement ARMv8.5-MemTag | expand

Commit Message

Richard Henderson Feb. 11, 2019, 1:08 a.m. UTC

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper-a64.h    | 1 +
 target/arm/mte_helper.c    | 6 ++++++
 target/arm/translate-a64.c | 6 ++++++
 3 files changed, 13 insertions(+)

-- 
2.17.2

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 47577207b2..ef340cb6f9 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -107,3 +107,4 @@  DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64)
 DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)
 DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32)
 DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32)
+DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 3eb5d622fc..fc9e172c95 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -234,3 +234,9 @@  uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr,
 
     return address_with_allocation_tag(ptr - offset, rtag);
 }
+
+uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask)
+{
+    int tag = allocation_tag_from_addr(ptr);
+    return mask | (1ULL << tag);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 3d71a9701f..2e0d797294 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5158,6 +5158,12 @@  static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
         gen_helper_irg(cpu_reg_sp(s, rd), cpu_env,
                        cpu_reg_sp(s, rn), cpu_reg(s, rm));
         break;
+    case 5: /* GMI */
+        if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
+            goto do_unallocated;
+        }
+        gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm));
+        break;
     case 8: /* LSLV */
         handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
         break;

[v2,12/26] target/arm: Implement the GMI instruction

Commit Message

Patch