From patchwork Sat Feb 9 03:38:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157911 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp241992jaa; Fri, 8 Feb 2019 19:47:15 -0800 (PST) X-Google-Smtp-Source: AHgI3IZbuC5/7pI9jl3kMa3MDiw1eAPMSItcxtTe4VOD7NefcR0tWKTCTFoKfPpCaZ0fC2GGnCqV X-Received: by 2002:a1c:7312:: with SMTP id d18mr543285wmb.24.1549684034993; Fri, 08 Feb 2019 19:47:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549684034; cv=none; d=google.com; s=arc-20160816; b=jze3W7czNpYxJZHa5y2obL6AcpsuRigW+N/CvqqQltOw/r8NWacHnkhcH03P2ezXG1 LAvDLsdejWLPYU+Yg4Xg3BJMSWWcq4S37duiDscsGsg+WSHUXoHJlr5cnI8+4MtdNu8U HILvfj6OlsBG994DiVz8Mq58qM7QavclT1MCV2a/ANtNMDTcfCjGM0Ogo0WzX2zn3oM9 Iy8vAY4aWyRkAHIfToNLJz2PHW615L6wW13I/w4LoSpsfmlGz9jnWiS0TMefWjPbx6// 7Gh4DE2gpbnoUKyEHjyhgtlzY5JDOLRupYakQ17C8MF8XTo/+yh6OPCQCaghMQPSAQgl hzAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aCH1tSuPlPTrUampigSo2Lvj/9ILp6juR6hIm3KXMeA=; b=Kx8ZLiWHtNSMfwX6NKTfAX4s+wmx2PRs0haALG+WuarvZLFzsmOptd8qRI3+tj+ELB +zWefnc+MwXe9QuIiqTiRyoJJ1txKEBkd8rky6CcGhzinSZa5QnUMhPFV9kmgGNchOof N0rNBiDaM62t5eQbtgqjGVSi5FxpR3LPkkygjXYOv39ROK91MqasUOoxDjHqXgMoc5Dy W+hHgzZvbCEby/Iv5VA6Mp3sZ3vhEj3E5C9zsVYlpQDN0l0ZjpSHLVG3qzRWrTzuVRQ3 Jn7Qql7nJdkg1dIeb3EJBEEzdQzp8BXvWY+i58Edmcplttnn5Mc7eFH+HK+n3PbMBEw5 LuDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dRTA+h+y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s3si3230735wre.290.2019.02.08.19.47.14 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 08 Feb 2019 19:47:14 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dRTA+h+y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39151 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gsJbl-0003wO-Ti for patch@linaro.org; Fri, 08 Feb 2019 22:47:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:42567) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gsJUY-0007PR-5r for qemu-devel@nongnu.org; Fri, 08 Feb 2019 22:39:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gsJUS-0000hn-CS for qemu-devel@nongnu.org; Fri, 08 Feb 2019 22:39:43 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:34539) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gsJUN-0000Wm-B5 for qemu-devel@nongnu.org; Fri, 08 Feb 2019 22:39:37 -0500 Received: by mail-pg1-x541.google.com with SMTP id d9so2432743pgl.1 for ; Fri, 08 Feb 2019 19:39:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aCH1tSuPlPTrUampigSo2Lvj/9ILp6juR6hIm3KXMeA=; b=dRTA+h+yP4AFsT+GkLCbLkKjpEeHsTfQ9AhrcRAavxuT6ddyBIwxdtkM85j41IvUOX lX3uZx3WhtXc3QAhHJd/5c5G492+CFO7SI9tNVKT/xizhXTlyXcYkJELgHynHqcl5hZL TrBjvzi2A4tB8NbcuL5GlJe79SBhymQHkYB0efxeIqyt/eD3IwG9fdNC+f4sKOkQ9JCu mIil97Fh3SvzVK8ufGPIC3rkjrUNQ6CkahgdtANJM9OJ+sWcUnezJjTfX6Fxg4LPbIWj DNJYOgN/2AViIU/4wtO+cKvB6obucqHZoNHgwAcxN4Vp1QlDnbShAKeDNZF1B71L6qlX vD2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aCH1tSuPlPTrUampigSo2Lvj/9ILp6juR6hIm3KXMeA=; b=DQwYB3KJNQqYOnf12QFyfB0ZF/4QK4T/ijtkdOAkg+5YstattbGkrGiIuPwonFRK1c rKJ0jA+eFHDcn5fIknXNv7O3LOfqEDtRXT9ErKtE+VeSekt1Yb+y/Y907x2d7BMybLeY hZNaGRel5njEa9Nrq3mBxxvIA5cITexNaYA6eYZfV3RdjLnW64jJWNz229xneh1T2S2k LYqlornGQcU2JWLxpufik/trMEa+Ue2Jn0pshS+M0seicr4O80KNDBmhWtAo4Po+k2NY wgjcH1RIRhw0Ok/N106PcyQkUGkDZQdcH24JclWEwXHt2NSLurz3q+nTOogLe9xhA1EA S0BA== X-Gm-Message-State: AHQUAuaqoTOBxuvwyZRbrL2ZQxaIV2qGiySFwRILRPV4D4VVHgZYoTuw xtHjM2LuQvVrMFVJ7zcpV964ELFSkvQ= X-Received: by 2002:a63:cc41:: with SMTP id q1mr8540399pgi.323.1549683546339; Fri, 08 Feb 2019 19:39:06 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.39.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:45 -0800 Message-Id: <20190209033847.9014-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 10/12] target/arm: Split out FPSCR.QC to a vector field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change the representation of this field such that it is easy to set from vector code. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++++- target/arm/helper.c | 19 +++++++++++++++---- target/arm/neon_helper.c | 2 +- target/arm/vec_helper.c | 2 +- 4 files changed, 21 insertions(+), 7 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47238e4245..b96463e8f1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -577,11 +577,13 @@ typedef struct CPUARMState { ARMPredicateReg preg_tmp; #endif - uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ + uint32_t qc[4] QEMU_ALIGNED(16); int vec_len; int vec_stride; + uint32_t xregs[16]; + /* Scratch space for aa32 neon expansion. */ uint32_t scratch[8]; @@ -1427,6 +1429,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ +#define FPCR_QC (1 << 27) /* Cumulative saturation bit */ static inline uint32_t vfp_get_fpsr(CPUARMState *env) { diff --git a/target/arm/helper.c b/target/arm/helper.c index af22274bd9..7ed9933663 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12585,8 +12585,7 @@ static inline int vfp_exceptbits_from_host(int host_bits) uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) { - int i; - uint32_t fpscr; + uint32_t i, fpscr; fpscr = env->vfp.xregs[ARM_VFP_FPSCR] | (env->vfp.vec_len << 16) @@ -12597,8 +12596,11 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) /* FZ16 does not generate an input denormal exception. */ i |= (get_float_exception_flags(&env->vfp.fp_status_f16) & ~float_flag_input_denormal); - fpscr |= vfp_exceptbits_from_host(i); + + i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3]; + fpscr |= i ? FPCR_QC : 0; + return fpscr; } @@ -12645,10 +12647,19 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) * (which are stored in fp_status), and the other RES0 bits * in between, then we clear all of the low 16 bits. */ - env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xffc80000; + env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000; env->vfp.vec_len = (val >> 16) & 7; env->vfp.vec_stride = (val >> 20) & 3; + /* + * The bit we set within fpscr_q is arbitrary; the register as a + * whole being zero/non-zero is what counts. + */ + env->vfp.qc[0] = val & FPCR_QC; + env->vfp.qc[1] = 0; + env->vfp.qc[2] = 0; + env->vfp.qc[3] = 0; + changed ^= val; if (changed & (3 << 22)) { i = (val >> 22) & 3; diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 3249005b62..ed1c6fc41c 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -15,7 +15,7 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) -#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q +#define SET_QC() env->vfp.qc[0] = 1 #define NEON_TYPE1(name, type) \ typedef struct \ diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 37f338732e..65a18af4e0 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -36,7 +36,7 @@ #define H4(x) (x) #endif -#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q +#define SET_QC() env->vfp.qc[0] = 1 static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) {