From patchwork Mon Jan 28 15:58:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 156778 Delivered-To: patch@linaro.org Received: by 2002:ac9:7558:0:0:0:0:0 with SMTP id r24csp3535910oct; Mon, 28 Jan 2019 08:14:43 -0800 (PST) X-Google-Smtp-Source: ALg8bN4P0pwOGcFBQodg+wjfnMwCJbUeteEaMEXfuSyMq11MbeCIQ0psueixEtnKjXsHWMXHU0wP X-Received: by 2002:a1c:7dd7:: with SMTP id y206mr17650424wmc.50.1548692083708; Mon, 28 Jan 2019 08:14:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548692083; cv=none; d=google.com; s=arc-20160816; b=aYsYh4oscq+JZaLOntLemro2cyjZP6bMXxlOLV60IqxR7qQqLqQahwcyKkNU3fhTHe cAq3JincggLsBQTl9j/ugkETwsEF/6bfcz8dy3Kq90jLVN6rgA1/TU8T6R3KKVrOdFSa yl+uvRV9/I77tWXo5fbR+7Lso/EhgeBec1HjrHwhoeFj7DN6rjlfL7eVLVrI18/QPJ+O IExIf9T09/CgFhVcj5ySFN3zTcxbu8IFzBTWuaS3e58KCfI5BAH5EGD0geplxQslm/vo IDUkmg08y2yxXup6u2QHpxDsRlEhAYnOC6o6bxYK4Qxjf1yKVygh7a/b/HZdaYJHpFNu ihFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=TqlRQyNLGQUtXCq+DygG9z0Ggqd2FQuVBMC93AMwhZk=; b=p2Y1fNgUwbBHJG+8w3Q/TwoXnjM7zWZwf1lIVos3j8lCslmm7etkjxfzacepnlFxCv 4vyb59PVdF7erinYfCqXTE+W/FtATfIopCePFl+szaidQOPEOD00rWtDGpyb1vAqABJ/ ovgwBCoJ1CMulTeSerm8/V6XqTZD86v4UhcGFpJfPXvsibRGc4KbS3E2gXeUFhtqHjhe uKGBwby9XN4b9zNGOfO9e3XClvjNDqeQ9I+Lp/UjyAAKE0zhwmwCkaSmiyNHyMBypjkc R3ULBNTTzAAn9DDGcQkh5ejaNn7enDrIrkT8uvOgPTJaCoRJOx6Vlkh1cnaq/etIr3e8 NYYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dHE4EOHR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w75si7312750wmf.95.2019.01.28.08.14.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 08:14:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dHE4EOHR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:34347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1go9YX-0007QN-Nb for patch@linaro.org; Mon, 28 Jan 2019 11:14:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:33418) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1go9Jj-0004so-I4 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 10:59:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1go9Ji-0007k3-HG for qemu-devel@nongnu.org; Mon, 28 Jan 2019 10:59:23 -0500 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:45044) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1go9Ji-0007jl-C2 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 10:59:22 -0500 Received: by mail-pg1-x531.google.com with SMTP id t13so7370193pgr.11 for ; Mon, 28 Jan 2019 07:59:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TqlRQyNLGQUtXCq+DygG9z0Ggqd2FQuVBMC93AMwhZk=; b=dHE4EOHRX8bUaF/vz2SDQZ/5+nBpKPGLolTFmRTubzYryYImF0kMxGArJoF46kNpHh vtplG45+1vYafXKTZ7XM989Iu/wySprjTMntHvzBl8+Z4H+9FnhBEfMEKweIvlhR5mhO AfLxwvhFq8drkgMU9uIiFFfgMypufdrekh4kk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TqlRQyNLGQUtXCq+DygG9z0Ggqd2FQuVBMC93AMwhZk=; b=APSkwq1TufG0yizkURpCbvz72eD2ZPM5wIo8gl6hJ+CmieLJXUZx53c/2CEw7Bzlx6 ZeagEWaZZeO7Y+5V5FBYwlanYm19IvapnPsDmKAeTIXdwt/E4syUj4INjFanj6xMhnpD xkf7pVQ2RqsXtK2RO8vW+HMafj5SeE/Uf/zHyKEYKNj/iDV9qi4gE8rK0eJVPk9u++Gk mwcYZZHFsgwrODK1qdDSeSt9v361CXruuV3Y526H1lWsm+mjyXA5BFZsNvJXdYEP/N3U SB6syDyy2kaExiIPYTnn37yAhsGbtkdsfg4hWz7nV8IUSX1/jIGyx/HNZ++kR53TLims jAFQ== X-Gm-Message-State: AJcUukeKFH+0IGG/HT/S5eSBYio+W9cSm0FyI8qccxfsNIx3JBMqab4F tU+Hi9cc59O6SY7sdwuk5dtH6Riu1Gk= X-Received: by 2002:a62:8a51:: with SMTP id y78mr22176191pfd.35.1548691160951; Mon, 28 Jan 2019 07:59:20 -0800 (PST) Received: from cloudburst.twiddle.net (50-233-235-3-static.hfc.comcastbusiness.net. [50.233.235.3]) by smtp.gmail.com with ESMTPSA id p2sm45518687pfp.125.2019.01.28.07.59.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 07:59:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 07:58:51 -0800 Message-Id: <20190128155907.20607-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128155907.20607-1-richard.henderson@linaro.org> References: <20190128155907.20607-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PULL 07/23] tcg/i386: Implement vector saturating arithmetic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only MO_8 and MO_16 are implemented, since that's all the instruction set provides. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 42 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7bd7eae672..efbd5a6fc9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -185,7 +185,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 6f4c16326f..a5791dfaa5 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -377,6 +377,10 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #define OPC_PADDW (0xfd | P_EXT | P_DATA16) #define OPC_PADDD (0xfe | P_EXT | P_DATA16) #define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) +#define OPC_PADDSB (0xec | P_EXT | P_DATA16) +#define OPC_PADDSW (0xed | P_EXT | P_DATA16) +#define OPC_PADDUB (0xdc | P_EXT | P_DATA16) +#define OPC_PADDUW (0xdd | P_EXT | P_DATA16) #define OPC_PAND (0xdb | P_EXT | P_DATA16) #define OPC_PANDN (0xdf | P_EXT | P_DATA16) #define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16) @@ -408,6 +412,10 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) #define OPC_PSUBD (0xfa | P_EXT | P_DATA16) #define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) +#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16) +#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16) +#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16) +#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16) #define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16) #define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16) #define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16) @@ -2591,9 +2599,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, static int const add_insn[4] = { OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ }; + static int const ssadd_insn[4] = { + OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 + }; + static int const usadd_insn[4] = { + OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2 + }; static int const sub_insn[4] = { OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ }; + static int const sssub_insn[4] = { + OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 + }; + static int const ussub_insn[4] = { + OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2 + }; static int const mul_insn[4] = { OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2 }; @@ -2631,9 +2651,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_add_vec: insn = add_insn[vece]; goto gen_simd; + case INDEX_op_ssadd_vec: + insn = ssadd_insn[vece]; + goto gen_simd; + case INDEX_op_usadd_vec: + insn = usadd_insn[vece]; + goto gen_simd; case INDEX_op_sub_vec: insn = sub_insn[vece]; goto gen_simd; + case INDEX_op_sssub_vec: + insn = sssub_insn[vece]; + goto gen_simd; + case INDEX_op_ussub_vec: + insn = ussub_insn[vece]; + goto gen_simd; case INDEX_op_mul_vec: insn = mul_insn[vece]; goto gen_simd; @@ -3007,6 +3039,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_or_vec: case INDEX_op_xor_vec: case INDEX_op_andc_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: case INDEX_op_cmp_vec: case INDEX_op_x86_shufps_vec: case INDEX_op_x86_blend_vec: @@ -3074,6 +3110,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) } return 1; + case INDEX_op_ssadd_vec: + case INDEX_op_usadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_ussub_vec: + return vece <= MO_16; + default: return 0; }