[13/17] target/arm: Set PSTATE.TCO on exception entry

Message ID	20190114011122.5995-14-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:18 +1100 Message-Id: <20190114011122.5995-14-richard.henderson@linaro.org> In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception entry Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Implement ARMv8.5-MemTag \| expand [00/17] target/arm: Implement ARMv8.5-MemTag [01/17] target/arm: Add MTE_ACTIVE to tb_flags [02/17] target/arm: Extract TCMA with ARMVAParameters [03/17] target/arm: Add MTE system registers [04/17] target/arm: Fill in helper_mte_check [05/17] target/arm: Suppress tag check for sp+offset [06/17] target/arm: Implement the IRG instruction [07/17] target/arm: Implement ADDG, SUBG instructions [08/17] target/arm: Implement the GMI instruction [09/17] target/arm: Implement the SUBP instruction [10/17] target/arm: Implement LDG, STG, ST2G instructions [11/17] target/arm: Implement the STGP instruction [12/17] target/arm: Implement the LDGV and STGV instructions [13/17] target/arm: Set PSTATE.TCO on exception entry [14/17] tcg: Introduce target-specific page data for user-only [15/17] target/arm: Add allocation tag storage for user-only [16/17] target/arm: Enable MTE [17/17] tests/tcg/aarch64: Add mte smoke tests

Message ID

20190114011122.5995-14-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 14 Jan 2019 12:11:18 +1100
Message-Id: <20190114011122.5995-14-richard.henderson@linaro.org>
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Subject: [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception
	entry
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Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
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Series

target/arm: Implement ARMv8.5-MemTag | expand

R0085 specifies that exception handlers begin with tag checks overridden. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.2

Comments

Peter Maydell Feb. 7, 2019, 5:44 p.m. UTC | #1

On Mon, 14 Jan 2019 at 01:12, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> R0085 specifies that exception handlers begin with tag checks overridden.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/helper.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index df43deb0f8..1e9ccf0b2e 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -8830,7 +8830,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)

>      qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",

>                    env->elr_el[new_el]);

>

> -    pstate_write(env, PSTATE_DAIF | new_mode);

> +    pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode);

>      env->aarch64 = 1;

>      aarch64_restore_sp(env, new_el);


PSTATE_TCO being set doesn't affect codegen for non-MTE CPUs,
right?

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM

Richard Henderson Feb. 8, 2019, 5:16 p.m. UTC | #2

On 2/7/19 9:44 AM, Peter Maydell wrote:
> On Mon, 14 Jan 2019 at 01:12, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>>

>> R0085 specifies that exception handlers begin with tag checks overridden.

>>

>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>> ---

>>  target/arm/helper.c | 2 +-

>>  1 file changed, 1 insertion(+), 1 deletion(-)

>>

>> diff --git a/target/arm/helper.c b/target/arm/helper.c

>> index df43deb0f8..1e9ccf0b2e 100644

>> --- a/target/arm/helper.c

>> +++ b/target/arm/helper.c

>> @@ -8830,7 +8830,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)

>>      qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",

>>                    env->elr_el[new_el]);

>>

>> -    pstate_write(env, PSTATE_DAIF | new_mode);

>> +    pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode);

>>      env->aarch64 = 1;

>>      aarch64_restore_sp(env, new_el);

> 

> PSTATE_TCO being set doesn't affect codegen for non-MTE CPUs,

> right?


TCO does not exist before MTE.  I shouldn't set it without MTE, I think, as
it's visible to the guest.

r~

diff --git a/target/arm/helper.c b/target/arm/helper.c
index df43deb0f8..1e9ccf0b2e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8830,7 +8830,7 @@  static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
                   env->elr_el[new_el]);
 
-    pstate_write(env, PSTATE_DAIF | new_mode);
+    pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode);
     env->aarch64 = 1;
     aarch64_restore_sp(env, new_el);

[13/17] target/arm: Set PSTATE.TCO on exception entry

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