From patchwork Tue Dec 18 06:38:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 154082 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3344722ljp; Mon, 17 Dec 2018 22:40:24 -0800 (PST) X-Google-Smtp-Source: AFSGD/UmNSgDB0bDgPiso+ayqFTLBeCsmo218g7BXkkzs1SuHzTQXdgI9fmiq/ZjgkFw1/o+ER7G X-Received: by 2002:a37:1ad9:: with SMTP id l86mr14470775qkh.54.1545115224364; Mon, 17 Dec 2018 22:40:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545115224; cv=none; d=google.com; s=arc-20160816; b=Zxw0rFY9UPqSRGMqm9a5smn3V/O4CVfAAbbQRrDjcaNIusdk6lLuaFM9Ph/1/XkuvW FR7FUuVrQqKInfxuRWZUE5cyfnV8X/x++Z4kA5Z+zbvxYT6ztfj+HRWc5FD6UF7WdMmr Nc8rxwpQwam4ikUOgeqSrXwXyDTAcOdCQNgdiWgjELMhEbi8OHN5qnFkjH5pWyAMfJYk YyGU4H6ruo0qGSqm9ychKg5ebnwNM+cGD7ECDYhRkM2znHqe21pwpzxvuuikU8iH2c5G 9/HV8uffBziDNhv+0WeCDccjvYi1zXGPNUT/+1Cu1n5SJrBjQUxBDiacjcffhnIAA9cq 3XWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=13baR0fYl6duiBYqIpKDqOz4EjDaN2cM4w2ffhmehW8=; b=vrKuupBvtx0DB0k5qwpdS8olqZbzXGM03TOAHbVaXmHbHiZL5NiUPO9XirXi/Rqp6G ScdZnIOtfT3b7tnKc0Ey4WQ25rEL9NbhjcO8KrJVSetvIw/TmFWn17Ne2kX1/hU7BPzF NmYA/P2mV+WdgJV/0yx44yb75j/BIj729BJQepErJ/ytgssU3kAGBDYDvER0mDUfbh5N hGbahAixbL0cvxxpNHqHQ/as72WPyYs/yOR+sYD29ujDZbEm9K8CZ7InR4uSdHSQmyRa b4CXvIkVhOo4p5Swm0/sH3Uc6BEmYWnNNJ0T1h2EJAOmtj7eI3EfalrSYzfI4t7Ivo5V 8Lfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SXfoBG7i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v2si1142700qvm.85.2018.12.17.22.40.24 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 17 Dec 2018 22:40:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SXfoBG7i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52013 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ93H-0001c1-KY for patch@linaro.org; Tue, 18 Dec 2018 01:40:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZ92X-0001O9-Se for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZ92U-00029J-Vv for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:37 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:44258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gZ92U-0001uj-6k for qemu-devel@nongnu.org; Tue, 18 Dec 2018 01:39:34 -0500 Received: by mail-pg1-x542.google.com with SMTP id t13so7333739pgr.11 for ; Mon, 17 Dec 2018 22:39:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=13baR0fYl6duiBYqIpKDqOz4EjDaN2cM4w2ffhmehW8=; b=SXfoBG7iMZmG/vXwlDheXCUNNDVjlGTnaEmexZW4Fe0rol23MnXI1yFzF+i7ci3mKB Ww7DkOOL2VJgczdn+7Hguc7K0Wx75OCMZYuINjT2RbKbWTDcRkKF3dkh4OO9ifuNsflV jqvt6mknF6vi0aO201YTlVQPd7m9OkeUE9/70= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=13baR0fYl6duiBYqIpKDqOz4EjDaN2cM4w2ffhmehW8=; b=TeQaMVv4GL7zI2MAwIPhpdtZvmR6pvonpGVIcfQT0F2xjUyoEsMLKkUuLGynnUtN1h r8EZUQuRtSI85V7DsHRTM74Sk8d21NI7gZubbrA7gztuOBbkc2Ju89ly4HxUylBjzjhV l38l3TeX6SUXNJRTVtQddOKK1pwm6YTjXLzYp6DJ3iDAOzyCSktMUnrAKzJpMIrHzpKc GBy3kW2wbZvMhznbXK9YKt5YcFhQ/fNJEjeWtgzWEvM0xiXLGfBeGehgWPLBQ6g1ukI+ 9H44a9S9ChfZ/O9s1EYkQNix3FZACN8cVUfQbhsrTVrzeLC2saLYab86HBw7VLs37dHa cLGQ== X-Gm-Message-State: AA+aEWau7zxh4U5tRJ0bCV3zTBdg2mJPG8cKkUVR09h64eZEtJESYCTf cvczH6BcAjaM2aSi9qCNjK3uvihBNB8= X-Received: by 2002:a63:de04:: with SMTP id f4mr14476267pgg.292.1545115158616; Mon, 17 Dec 2018 22:39:18 -0800 (PST) Received: from cloudburst.twiddle.net (97-126-115-157.tukw.qwest.net. [97.126.115.157]) by smtp.gmail.com with ESMTPSA id c7sm27072509pfh.18.2018.12.17.22.39.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Dec 2018 22:39:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Dec 2018 22:38:41 -0800 Message-Id: <20181218063911.2112-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181218063911.2112-1-richard.henderson@linaro.org> References: <20181218063911.2112-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 04/34] tcg: Add write_aofs to GVecGen4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, mark.cave-ayland@ilande.co.uk, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows writing 2 output, 3 input operations. Signed-off-by: Richard Henderson --- tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op-gvec.c | 27 +++++++++++++++++++-------- 2 files changed, 21 insertions(+), 8 deletions(-) -- 2.17.2 diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index d65b9d9d4c..2cb447112e 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -181,6 +181,8 @@ typedef struct { uint8_t vece; /* Prefer i64 to v64. */ bool prefer_i64; + /* Write aofs as a 2nd dest operand. */ + bool write_aofs; } GVecGen4; void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 81689d02f7..c10d3d7b26 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -665,7 +665,7 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs, /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t oprsz, + uint32_t cofs, uint32_t oprsz, bool write_aofs, void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32)) { TCGv_i32 t0 = tcg_temp_new_i32(); @@ -680,6 +680,9 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_gen_ld_i32(t3, cpu_env, cofs + i); fni(t0, t1, t2, t3); tcg_gen_st_i32(t0, cpu_env, dofs + i); + if (write_aofs) { + tcg_gen_st_i32(t1, cpu_env, aofs + i); + } } tcg_temp_free_i32(t3); tcg_temp_free_i32(t2); @@ -769,7 +772,7 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs, /* Expand OPSZ bytes worth of three-operand operations using i64 elements. */ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t oprsz, + uint32_t cofs, uint32_t oprsz, bool write_aofs, void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { TCGv_i64 t0 = tcg_temp_new_i64(); @@ -784,6 +787,9 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, tcg_gen_ld_i64(t3, cpu_env, cofs + i); fni(t0, t1, t2, t3); tcg_gen_st_i64(t0, cpu_env, dofs + i); + if (write_aofs) { + tcg_gen_st_i64(t1, cpu_env, aofs + i); + } } tcg_temp_free_i64(t3); tcg_temp_free_i64(t2); @@ -880,7 +886,7 @@ static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs, /* Expand OPSZ bytes worth of four-operand operations using host vectors. */ static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, uint32_t oprsz, - uint32_t tysz, TCGType type, + uint32_t tysz, TCGType type, bool write_aofs, void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec)) { @@ -896,6 +902,9 @@ static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs, tcg_gen_ld_vec(t3, cpu_env, cofs + i); fni(vece, t0, t1, t2, t3); tcg_gen_st_vec(t0, cpu_env, dofs + i); + if (write_aofs) { + tcg_gen_st_vec(t1, cpu_env, aofs + i); + } } tcg_temp_free_vec(t3); tcg_temp_free_vec(t2); @@ -1187,7 +1196,7 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, */ some = QEMU_ALIGN_DOWN(oprsz, 32); expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some, - 32, TCG_TYPE_V256, g->fniv); + 32, TCG_TYPE_V256, g->write_aofs, g->fniv); if (some == oprsz) { break; } @@ -1200,18 +1209,20 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, /* fallthru */ case TCG_TYPE_V128: expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, - 16, TCG_TYPE_V128, g->fniv); + 16, TCG_TYPE_V128, g->write_aofs, g->fniv); break; case TCG_TYPE_V64: expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, - 8, TCG_TYPE_V64, g->fniv); + 8, TCG_TYPE_V64, g->write_aofs, g->fniv); break; case 0: if (g->fni8 && check_size_impl(oprsz, 8)) { - expand_4_i64(dofs, aofs, bofs, cofs, oprsz, g->fni8); + expand_4_i64(dofs, aofs, bofs, cofs, oprsz, + g->write_aofs, g->fni8); } else if (g->fni4 && check_size_impl(oprsz, 4)) { - expand_4_i32(dofs, aofs, bofs, cofs, oprsz, g->fni4); + expand_4_i32(dofs, aofs, bofs, cofs, oprsz, + g->write_aofs, g->fni4); } else { assert(g->fno != NULL); tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,