From patchwork Mon Dec 3 20:38:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 152742 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7272617ljp; Mon, 3 Dec 2018 12:44:18 -0800 (PST) X-Google-Smtp-Source: AFSGD/WLs6X+W1InmoqugokCZ2aQ9MzitWxMtDaOEgz6JLmOIOSC/91cAA9xIstG28aF1GiZUMi4 X-Received: by 2002:ac8:7201:: with SMTP id a1mr16823504qtp.291.1543869858618; Mon, 03 Dec 2018 12:44:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543869858; cv=none; d=google.com; s=arc-20160816; b=oY/s/V1zOwoA0Htj6CwZtId/ba39TAo6MMd/94ZMrHcx7d8iMfxBkXs6Sqpu8n5chk JycspphrdptX2pv3kctuN8WxNttcowbkn8KZ5eounRQ/0ilKpkuWU+6o16XW9NLniXbh loKI/1Vimibt+gJ+5oZMT6xNFqMt/zv1fKA9mweshWcOlPfKhI3x0hTLHeauuG2QmTz6 aqBTN8t6fvBOARO1iCxtKZ5JclM1ZztWWtABQvWG/0DSMMXQRWx5opB4+mIPw9AKS7Zx 996GnqbgbD9LUX0USAiJI3fzDyTfil5bAMsmnbBK5oAPMyAglGh5gjCVSXp58+BuQp/B Tgxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HgiPURpwkuNHglqGFtsbvHALu/51kR4r/LhZdFeceZ4=; b=hRVYLzTEpXjIAAk0k9KTAwsXk0hvICAMVJ5vxpB47Lhkdc/EzOqNuscZth32DtdSp4 2ZxKQjKSQ/9rxC9AZR7g3HdprC+TAiraABaXzrOesvUzSApO2T5D8EOU2xeGQyn0j1Q7 JVatl1jMDOojIYAVGJcptLPjXn8pcNMMB5ueiv4wkVCI04Xc1A/PB31IzeRnR+6fS6Wl UwIIxYAvJ54CqrYyxXFmCYGvvE03YORShDoi+IUHeaYZ+QLYkDI6AT+PomkZPjf+HEqW gYniPhvPFE0IhBIJJtR2q40jVy8aPP/PV6LZfBJqD4NY9IELnzuNLWUAsIZWOc/kxXnt EFtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UUASMDz4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o135si9337700qke.7.2018.12.03.12.44.18 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 03 Dec 2018 12:44:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UUASMDz4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52379 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv4k-0001S9-1N for patch@linaro.org; Mon, 03 Dec 2018 15:44:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42260) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzR-0005zH-D8 for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzO-0005ZZ-9F for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:49 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:36332) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzO-0005YZ-4B for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:46 -0500 Received: by mail-ot1-x344.google.com with SMTP id k98so12988440otk.3 for ; Mon, 03 Dec 2018 12:38:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HgiPURpwkuNHglqGFtsbvHALu/51kR4r/LhZdFeceZ4=; b=UUASMDz4Cb7gfyNRGUH/Z7bWnRUISHp7nCq1GLtM7wQPAE8nMRSbnCwb978qI7uaOi oQ2rYo99L6N5zhMWb726xvV0N8Wf8zz+cerBkG8NezW4DK62W9+1QrSZwjbArSrxfjgR aUEO0MTHRWiQ0LpLC1bc7BbPNUSHsBXvkImGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HgiPURpwkuNHglqGFtsbvHALu/51kR4r/LhZdFeceZ4=; b=fHpg+aZ/wkgTa+5g+zkOAsDKUWSj852EeTtR+eJOfC46k0iv3O/wblDa4+JN6S+ium gwOxAFkD9ZsZTaD9tjqb+ouPjJBiWZDlZUoBnDToVeSzx+4YKGHOEyh4WbMNUEj4AC77 aSck5lcvbfX8w2qn4T24sISEKzU58fC8e12Pkpg4pfcSQ5yWsMzn8ygHJiMLznurQ/90 fmX0EYhibAIxMeVihMVDLmt2voC4/smMkufIsWz8+vML6d92BMGieG9yBvB5K7zXY6iC q6MEEeb6vk6OH3jH2zkogrdLAOn9/xMlPZqFjvSpXLgu0LyOw8BJ/J02AB8qOwyfAH+g 3vIw== X-Gm-Message-State: AA+aEWZISLfRd0PoWCvVu1hXbg6rJvmv7SdE4fQFRNlNX967N/de0ogd MgFz/YpMcUw90PIhn0cS2pf/EC+80gA= X-Received: by 2002:a9d:8c6:: with SMTP id 64mr11674292otf.168.1543869525050; Mon, 03 Dec 2018 12:38:45 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:30 -0600 Message-Id: <20181203203839.757-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 01/10] target/arm: Move id_aa64mmfr* to ARMISARegisters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, define the fields for these registers, and use those defines in arm_pamax(). Signed-off-by: Richard Henderson ---- v2: Include the v8.5 fields; init the registers for kvm. Upcase all of the field names. --- target/arm/cpu.h | 26 ++++++++++++++++++++++++-- target/arm/internals.h | 3 ++- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 4 ++++ 5 files changed, 35 insertions(+), 8 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2a73fed9a0..656a96a8f8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -818,6 +818,8 @@ struct ARMCPU { uint64_t id_aa64isar1; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; + uint64_t id_aa64mmfr0; + uint64_t id_aa64mmfr1; } isar; uint32_t midr; uint32_t revidr; @@ -839,8 +841,6 @@ struct ARMCPU { uint64_t id_aa64dfr1; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint64_t id_aa64mmfr0; - uint64_t id_aa64mmfr1; uint32_t dbgdidr; uint32_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ @@ -1557,6 +1557,28 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64MMFR0, PARANGE, 0, 4) +FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) +FIELD(ID_AA64MMFR0, BIGEND, 8, 4) +FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) +FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) +FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) +FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) +FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) +FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) +FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) +FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) +FIELD(ID_AA64MMFR0, EXS, 44, 4) + +FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) +FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) +FIELD(ID_AA64MMFR1, VH, 8, 4) +FIELD(ID_AA64MMFR1, HPDS, 12, 4) +FIELD(ID_AA64MMFR1, LO, 16, 4) +FIELD(ID_AA64MMFR1, PAN, 20, 4) +FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) +FIELD(ID_AA64MMFR1, XNX, 28, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/internals.h b/target/arm/internals.h index d208b70a64..78e026d6e9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -229,7 +229,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) [4] = 44, [5] = 48, }; - unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); + unsigned int parange = + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); /* id_aa64mmfr0 is a read-only register so values outside of the * supported mappings can be considered an implementation error. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 873f059bf2..0babe483ac 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,7 +141,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->pmceid0 = 0x00000000; cpu->pmceid1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001124; + cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ @@ -195,7 +195,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_aa64pfr0 = 0x00002222; cpu->id_aa64dfr0 = 0x10305106; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ + cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ @@ -249,7 +249,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->pmceid0 = 0x00000000; cpu->pmceid1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001124; + cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0da1424f72..04c4a91b04 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5207,11 +5207,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = cpu->id_aa64mmfr0 }, + .resetvalue = cpu->isar.id_aa64mmfr0 }, { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = cpu->id_aa64mmfr1 }, + .resetvalue = cpu->isar.id_aa64mmfr1 }, { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 0a502091e7..ad83e1479c 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -538,6 +538,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 6, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |= read_sys_reg64(fdarray[2], &achf->isar.id_aa64mmfr0, + ARM64_SYS_REG(3, 0, 0, 7, 0)); + err |= read_sys_reg64(fdarray[2], &achf->isar.id_aa64mmfr1, + ARM64_SYS_REG(3, 0, 0, 7, 1)); /* * Note that if AArch32 support is not present in the host,