From patchwork Fri Nov 23 14:45:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 151887 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2217016ljp; Fri, 23 Nov 2018 06:55:21 -0800 (PST) X-Google-Smtp-Source: AJdET5dzSccd79i0+mSuSbTUSy2U6w+ZQFV9We6oI27zNgqDkpnW7q9jhsbHrdqGkd+1jn2EZCEk X-Received: by 2002:a81:3906:: with SMTP id g6-v6mr17111974ywa.123.1542984921777; Fri, 23 Nov 2018 06:55:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542984921; cv=none; d=google.com; s=arc-20160816; b=z1k3N7vyfVm26hzoNy/JVnZk9YAsYpL+SQZmPhVMDqVErByGfErP6kYgRel5vWgQfK MrhioBUSSVeJwMqGMHdUdkTgSXZl5K276wkh5sewchgHcXbL0sIcJsJ7tpsADdBHXu6J 5/ryUXYboYAMotqrE4/seYVuqjhd5Domw6OJztzySMWWd+j4QMBWcU6A3zW9ukdfKVuO bApRuhS8ldJW0wfFN+9JaTXTbVwrSLMEqpOVVoIfV1T2Wh4ylBE84y2xegr3xlvwmZO6 iCyNUu9niiTH82rNJdsI2ewzH7ie7Ux7mz0YXUSpsL4TBHvx8J3ykoZKGAMf+fJxG65G lK/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=81OeRW7ulziampPD+KOnmfbUyMMOUlVeu4i4kj52zbk=; b=FYDwVDyoJQW4kZ6feFgtRgiY/RlkrYu/RmWGhTP7zDFFZZzaulJEaixvf5HQIDHUUO SZSJZzh+kvY6bKsatByzS83yQk9U9iA7NM8MNbdnmWEl9BM13b29j55W9zsGeZNdVbGa cx3Avf67+oYj0LlbKr6clBKGefOiYiWf0iOVfHMhUd/o1wPFWs5NE+qOWM1UnJ79y/ER PpsUbzcoY7Fj8pT2+IiHhTGCjAfFLesW7PkKciwiK05rQ5loNQxwEalubbKlmi13WLcH EsBNZTwbugW1pUP3MBoWdXLJYa7ByUXjR7NlsQ7qTvpC1jokSc7HJ0aRKATSLMaaiUw1 rZ/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g9xQMxzV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i6-v6si35393845ybh.166.2018.11.23.06.55.21 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 23 Nov 2018 06:55:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g9xQMxzV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52802 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCrZ-00011J-5z for patch@linaro.org; Fri, 23 Nov 2018 09:55:21 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43822) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gQCih-0007yd-4z for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gQCif-0003Ab-Q7 for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:11 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:38777) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gQCif-000384-II for qemu-devel@nongnu.org; Fri, 23 Nov 2018 09:46:09 -0500 Received: by mail-wm1-x341.google.com with SMTP id k198so12261530wmd.3 for ; Fri, 23 Nov 2018 06:46:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=81OeRW7ulziampPD+KOnmfbUyMMOUlVeu4i4kj52zbk=; b=g9xQMxzVkTkCohHfoZiNmGPHNlO1kA/TboWANDMJOWl5rHIX8J5lqJUc1MThPmf3OK YoNe6dWyXTxQE/YNWtaaiB3tXcwUC5l8J+ksl+bj6V8rtXJyREEF5VxAxJf0gbvVr2m6 /XdYCYb+yd4zRSjC4D0ioMuxljxlmY+KOz86Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=81OeRW7ulziampPD+KOnmfbUyMMOUlVeu4i4kj52zbk=; b=QfHo55WJklCkQ0hAAkVg25OuQAhpIplrcPVpodR77pgG+I/fLWuyFOV1QtRIUEA7nK +LOhmVXlqnapdmG9VSWvP/PVe/UXbk7d5Olyy/Qacsxlg1HBA+5Hu3t3uEEVgosVRUGA tUXZTkRW63skCuFedXzWp1aUOZj2C8ly6hyvlo/KRBsx0evLILQDowK3QV5ds7jEfiIf iy7h4QxQSWfnik5FECk//JhN25Yyxzqngx8IwtnZ9LtsQfhwN4hkxUpeRUKcC5YuAJ0t YMvzxjkiF/K9+ltNfvHiO6tf3J7uKLnmc0I/Xk8jrsfNEw3gFxuHjg75NlCJY40mpFzR +xow== X-Gm-Message-State: AGRZ1gKcFcowgnwuyUZGcm2dPMSSovk8exuanBNMq7s5e9+ZpgipxD+t NNbbyFbAwLKd7hXNLzS7dj5OFClOALba5A== X-Received: by 2002:a1c:9f8f:: with SMTP id i137mr13672918wme.30.1542984366699; Fri, 23 Nov 2018 06:46:06 -0800 (PST) Received: from cloudburst.twiddle.net ([195.77.246.50]) by smtp.gmail.com with ESMTPSA id p74sm10339630wmd.29.2018.11.23.06.46.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Nov 2018 06:46:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2018 15:45:27 +0100 Message-Id: <20181123144558.5048-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181123144558.5048-1-richard.henderson@linaro.org> References: <20181123144558.5048-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH for-4.0 v2 06/37] tcg/i386: Return a base register from tcg_out_tlb_load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly be asking the hot path not to assume TCG_REG_L1 for the host base address. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 56 ++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 27 deletions(-) -- 2.17.2 Reviewed-by: Alex Bennée diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 8aef66e430..3234a8d8bf 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1614,9 +1614,9 @@ static void * const qemu_st_helpers[16] = { First argument register is clobbered. */ -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - int mem_index, TCGMemOp opc, - tcg_insn_unit **label_ptr, int which) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, + int mem_index, TCGMemOp opc, + tcg_insn_unit **label_ptr, int which) { const TCGReg r0 = TCG_REG_L0; const TCGReg r1 = TCG_REG_L1; @@ -1696,6 +1696,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, /* add addend(r0), r1 */ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, offsetof(CPUTLBEntry, addend) - which); + + return r1; } /* @@ -2001,10 +2003,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif datalo = *args++; datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); @@ -2014,17 +2012,21 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - mem_index = get_mmuidx(oi); + { + int mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr[2]; + TCGReg base; - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); + base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_read)); - /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + /* TLB Hit. */ + tcg_out_qemu_ld_direct(s, datalo, datahi, base, -1, 0, 0, opc); - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Record the current context of a load into ldst label */ + add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); + } #else { int32_t offset = guest_base; @@ -2141,10 +2143,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; TCGMemOp opc; -#if defined(CONFIG_SOFTMMU) - int mem_index; - tcg_insn_unit *label_ptr[2]; -#endif datalo = *args++; datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); @@ -2154,17 +2152,21 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - mem_index = get_mmuidx(oi); + { + int mem_index = get_mmuidx(oi); + tcg_insn_unit *label_ptr[2]; + TCGReg base; - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); + base = tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + label_ptr, offsetof(CPUTLBEntry, addr_write)); - /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc); + /* TLB Hit. */ + tcg_out_qemu_st_direct(s, datalo, datahi, base, 0, 0, opc); - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + /* Record the current context of a store into ldst label */ + add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, + s->code_ptr, label_ptr); + } #else { int32_t offset = guest_base;