From patchwork Thu Nov 8 17:52:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 150564 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1142146ljp; Thu, 8 Nov 2018 10:02:04 -0800 (PST) X-Google-Smtp-Source: AJdET5df1vKBf62jz4wcOcXIh+Ig9N2ZmAGkiacJkcIAFiFZk3Ae9yVPs2okA0KSOI/2L6GOVWCZ X-Received: by 2002:ae9:e311:: with SMTP id v17mr4936319qkf.193.1541700124411; Thu, 08 Nov 2018 10:02:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541700124; cv=none; d=google.com; s=arc-20160816; b=ZXWwJmPnrPh6H93n42K9oqFjIIkQoTIMG25b5LyDhUYljL5HTGR+GdXxUUi6VMhY7/ /O3lJG9eg+SC7prgVF56qbPp7AeqPFNL6opKmqQZgUymu4lDz4UmNnOciA0sj9M3u6OT 9IiS7ixSZIr+zK/atHVgym9cgwJqU1eN9tdGPkEjHTGCED9jirmzipz7pT/ep8oM7vvd gtL2NeeOmN3BSmzHEAMqvD3KdOyhQLtEGGCAPSyM+2bdxOEk1kWBzhygRYNb0JRt7S1M Z0iTqVZAzNSr/Zgs4nvQDTkZjUXld/bULqtVvT0hbxinYYW1qyJlvrGW/Zxelk7Di7ep C1zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=6uQuU327VC/BRal1lZ+nVzurXjaVdMxrSfBdC83uyXQ=; b=ztiRYtDzemG0LAJ9IQd6RNA6JXDAupFEUwMz9qDmtg7iGH+B99xmNFjLGEUvIkZdia crgdFT2VQBgFdFHSnk7WkG4WvQbXwrvAvkMU03mkvxy+Kj+WTMDzl+irJTV4JD9/iKlS I1Elt6jlvZ1SSQ3ueKrhWdkGIN+qxx7abqRsNIr3t9mO3RetgVWlTOSTITcSWFa24grK CT7OM9FZNrK327l4W2bp7cU/mNnD/GkvELKT0bCLs87Lmo1nq80drmcUuYLMeOxoYQB+ eB0In7e0d4iNnq+X+bXL+BbPegYVMfF+xgraxpsVeGq2p33qo9a3OdB5DU3nDVl0wzkW exkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AdXeHyjb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g11si815453qth.320.2018.11.08.10.02.04 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Nov 2018 10:02:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AdXeHyjb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58376 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKod1-0008Od-Ur for patch@linaro.org; Thu, 08 Nov 2018 13:02:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gKoW8-0001c7-Dg for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gKoW4-0008AR-PY for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:56 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:40272) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gKoW4-00089z-Il for qemu-devel@nongnu.org; Thu, 08 Nov 2018 12:54:52 -0500 Received: by mail-wr1-x441.google.com with SMTP id i17-v6so22220236wre.7 for ; Thu, 08 Nov 2018 09:54:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6uQuU327VC/BRal1lZ+nVzurXjaVdMxrSfBdC83uyXQ=; b=AdXeHyjb4bhTngj2jOmlKAc+dTMxjLHweNLh6SHBSnPE0K3GeEmT3U3xirg7jyd1e/ 9umS4anC7dFpYyxGLE2d4zVVd+OS/aj2jO//ZoznjvfVngGp2SyF9ux/HAxeZ4DZXxBo DDOyDu+DmeJplsM5Wuhk/URBVkdQMAhYMXx6k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6uQuU327VC/BRal1lZ+nVzurXjaVdMxrSfBdC83uyXQ=; b=qYLY/WeiFlAyrhPG8/24BXjXeyRjd0GrlbuBu3i/94UismyNRZoael7qc7Of4AxoAq j8Xe/7akM0wN5Nll+UZ++q35ODcP4T0YZEXL9bR5lmOfZEFTM7p5zykshbQzZFozpn5t xn5hsCP74Pj6VAOgzjPrs+hu2wjsmAotnQKWD6sSN5/JfRaZeqiL8SY6PDAcHZIVH1vU MsqOIBqjNAqoMaVwdOrTWN/JW9MYDDMJ35smLNDYn27VOo1VOiOyNaIcsAjLZkl3nmLj BwPWdVMoLF2zYHmDoUWdTCdg9LSC8AlRZs1LkicDd/TPRGE8inKwH7bkNepfVqnJjUO1 nhKQ== X-Gm-Message-State: AGRZ1gJTnfqE6vQCgOldzk3Ny+BzrPyNa+em6qlu+I3S74YAMCs26d8v PxBKD0Qv7kMxiyeOwyYcuXaGsS0JLYeHRg== X-Received: by 2002:adf:fb12:: with SMTP id c18-v6mr5172342wrr.200.1541699691212; Thu, 08 Nov 2018 09:54:51 -0800 (PST) Received: from cloudburst.twiddle.net (70.red-2-141-114.dynamicip.rima-tde.net. [2.141.114.70]) by smtp.gmail.com with ESMTPSA id l42-v6sm4411384wre.37.2018.11.08.09.54.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Nov 2018 09:54:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Nov 2018 18:52:43 +0100 Message-Id: <20181108175246.13416-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181108175246.13416-1-richard.henderson@linaro.org> References: <20181108175246.13416-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v3 2/5] target/arm: Fill in ARMISARegisters for kvm64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 88 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5de8ff0ac5..e1128b94b2 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -443,17 +443,40 @@ static inline void unset_feature(uint64_t *features, int feature) *features &= ~(1ULL << feature); } +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); + err = ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + *pret = ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. - * For AArch64 we currently don't care about ID registers at - * all; we just want to know the CPU type. */ int fdarray[3]; uint64_t features = 0; + int err; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. Fortunately these old kernels @@ -474,8 +497,71 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ahcf->target = init.target; ahcf->dtb_compatible = "arm,arm-v8"; + err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + if (unlikely(err < 0)) { + /* + * Before v4.15, the kernel only exposed a limited number of system + * registers, not including any of the interesting AArch64 ID regs. + * For the most part we could leave these fields as zero with minimal + * effect, since this does not affect the values seen by the guest. + * + * However, it could cause problems down the line for QEMU, + * so provide a minimal v8.0 default. + * + * ??? Could read MIDR and use knowledge from cpu64.c. + * ??? Could map a page of memory into our temp guest and + * run the tiniest of hand-crafted kernels to extract + * the values seen by the guest. + * ??? Either of these sounds like too much effort just + * to work around running a modern host kernel. + */ + ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ + err = 0; + } else { + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + + /* + * Note that if AArch32 support is not present in the host, + * the AArch32 sysregs are present to be read, but will + * return UNKNOWN values. This is neither better nor worse + * than skipping the reads and leaving 0, as we must avoid + * considering the values in every case. + */ + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + } + kvm_arm_destroy_scratch_host_vcpu(fdarray); + if (err < 0) { + return false; + } + /* We can assume any KVM supporting CPU is at least a v8 * with VFPv4+Neon; this in turn implies most of the other * feature bits.