From patchwork Fri Oct 19 06:06:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149226 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp2908216lji; Thu, 18 Oct 2018 23:13:35 -0700 (PDT) X-Google-Smtp-Source: ACcGV62E3Di4YYZinjDQ0VC+t0ECbTVC/aP9L5E/KTSkboyg03tnCLiIn20/cGHIg7aroMQBD9dj X-Received: by 2002:ac8:7c6:: with SMTP id m6-v6mr32712743qth.365.1539929615719; Thu, 18 Oct 2018 23:13:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539929615; cv=none; d=google.com; s=arc-20160816; b=pQcgmKt9baC2E0GjTliGiGEYFixE/pOJ5Dr/pXVYKNCdodmXey/oT2njb3zrjDs1xw 9Q/1QiXb8sYVK8T4JnOapKja/YPw5LVw2hLKJoBriNBwkrID5pfM32pJm61+xDSP1Ubu qT4BX99RxoL+lLQGXOJYqQyxXPBht119AQ1/I9kJUC34pJqIP3GaAJFoKvNRm8DroVlm gcnXO2AZ86ZkXNATomlWi+YC3f1N5F1Aln9Scyc4EZzVgntYvT10YAnORDd7B71jbdVU 0blHIAP1IfqLtiS+RvlrKeFkoAP0XHg0XKXQ+9DxXqoQDZNf2qvhu67LAS4kvvMBQB4b 2D7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=o+dgHPD7vn5MSQoXXXAwqx0gYM5oyfE8kduesNuHmck=; b=IN8MYEw6T/ZnBYibczgbTnlB1jsEiNc0XoQ2LMLPhFegAdY96Mm0dF3SB+OhqymHOQ EGxFsQADeG7dLx4ZqwXgcaWWyia/pk4uwvgrWz2ePT6jaxOTIymx0F0YaXt2ZGScgR2B dTCKqCpUnOQ+enBCcQkqJt1ufp9cYouky5nDMyAyePuY3458vXHEfHPjiDUloypgnDsd irVN8AwTK4/NPro4DTTwq7tLm1mvpzyHTSrtSwtPLcFzz04PBbOn13orkvrCCdp6VR1h Nc1VxNP+OgzFlYrx2EBoW62OdBe0XBjLUNaWkTjD+C+NfvEtzhkvnekvWrnCJOS2o6eT 5tAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KzXpLAqa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a20-v6si7213173qtj.202.2018.10.18.23.13.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 18 Oct 2018 23:13:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KzXpLAqa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47248 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDO2R-0001p0-3D for patch@linaro.org; Fri, 19 Oct 2018 02:13:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDNwk-0004Ts-3t for qemu-devel@nongnu.org; Fri, 19 Oct 2018 02:07:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDNwg-0002o9-D1 for qemu-devel@nongnu.org; Fri, 19 Oct 2018 02:07:41 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:44959) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gDNwf-0002JS-Sy for qemu-devel@nongnu.org; Fri, 19 Oct 2018 02:07:38 -0400 Received: by mail-pl1-x644.google.com with SMTP id d23-v6so1955305pls.11 for ; Thu, 18 Oct 2018 23:07:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=o+dgHPD7vn5MSQoXXXAwqx0gYM5oyfE8kduesNuHmck=; b=KzXpLAqaEfJ5IzfTvJ+FuvgUI4xYmNy21w3kmpewuLIEd1SfG8JWe/P2HegGMVVqBr GXbRb62zR4OLwQE7UIfxURNPrtCJG8lO97lc+7Yw7FkXvwueHTtTw4JqE4bmRTzGNR0v K1coMDd6ehxjMf7SKevvtlpTam8O32PqUq1ys= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=o+dgHPD7vn5MSQoXXXAwqx0gYM5oyfE8kduesNuHmck=; b=HvjPKv2LplxN0NlmlWGr6n99pvBnKNP2NmuzwdGVcb1Ts28NaVsCTGBtulc0d0k6Iz fe1kNPsXm1p4sJN0cBj7/KxgkD/FEQ5Lv4gGurGtMU5/E0NMMCeSiKtEb92ixqkIl/+f ir6mRw/CB4lBxOeOpBRho/+z6jLvcA48rtjSBMQwx5QIIu3UPQhmnDC3bYRC+UXB+cmW YkfWFm/DyrH42+W5gPDBYxCALq2YVT/G+cgadpkzgxoig5SmZN5uhg3dATN7pyb4GVbh u6GBZVRfQvQjC1DmgkHB87HaSEF9QfnVmA0etr4n8u3FoUR6UoFBQMppRWVdOoAc5r2N g39Q== X-Gm-Message-State: ABuFfohite31Mo4g4jnIqnI23uDRNiVDaxyHZ5of+qR9Mdn26qApDmCL 25x9Np/1ZivU12SBkVUtgZX+g4UTCbc= X-Received: by 2002:a17:902:24e7:: with SMTP id l36-v6mr32733648plg.234.1539929242097; Thu, 18 Oct 2018 23:07:22 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id q24-v6sm25609327pff.83.2018.10.18.23.07.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 23:07:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 23:06:52 -0700 Message-Id: <20181019060656.7968-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019060656.7968-1-richard.henderson@linaro.org> References: <20181019060656.7968-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PULL v2 17/21] target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 92 +++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 51 deletions(-) -- 2.17.2 diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index bacae4f503..e106f61b4e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" #if !defined(CONFIG_USER_ONLY) #include "hw/s390x/storage-keys.h" @@ -1389,7 +1390,7 @@ static void do_cdsg(CPUS390XState *env, uint64_t addr, bool fail; if (parallel) { -#ifndef CONFIG_ATOMIC128 +#if !HAVE_CMPXCHG128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else int mem_idx = cpu_mmu_index(env, false); @@ -1435,9 +1436,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { -#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128) uint32_t mem_idx = cpu_mmu_index(env, false); -#endif uintptr_t ra = GETPC(); uint32_t fc = extract32(env->regs[0], 0, 8); uint32_t sc = extract32(env->regs[0], 8, 8); @@ -1465,18 +1464,20 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, probe_write(env, a2, 0, mem_idx, ra); #endif - /* Note that the compare-and-swap is atomic, and the store is atomic, but - the complete operation is not. Therefore we do not need to assert serial - context in order to implement this. That said, restart early if we can't - support either operation that is supposed to be atomic. */ + /* + * Note that the compare-and-swap is atomic, and the store is atomic, + * but the complete operation is not. Therefore we do not need to + * assert serial context in order to implement this. That said, + * restart early if we can't support either operation that is supposed + * to be atomic. + */ if (parallel) { - int mask = 0; -#if !defined(CONFIG_ATOMIC64) - mask = -8; -#elif !defined(CONFIG_ATOMIC128) - mask = -16; + uint32_t max = 2; +#ifdef CONFIG_ATOMIC64 + max = 3; #endif - if (((4 << fc) | (1 << sc)) & mask) { + if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || + (HAVE_ATOMIC128 ? 0 : sc > max)) { cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } } @@ -1546,16 +1547,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, Int128 cv = int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 ov; - if (parallel) { -#ifdef CONFIG_ATOMIC128 - TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - ov = helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); - cc = !int128_eq(ov, cv); -#else - /* Note that we asserted !parallel above. */ - g_assert_not_reached(); -#endif - } else { + if (!parallel) { uint64_t oh = cpu_ldq_data_ra(env, a1 + 0, ra); uint64_t ol = cpu_ldq_data_ra(env, a1 + 8, ra); @@ -1567,6 +1559,13 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); + } else if (HAVE_CMPXCHG128) { + TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + ov = helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); + cc = !int128_eq(ov, cv); + } else { + /* Note that we asserted !parallel above. */ + g_assert_not_reached(); } env->regs[r3 + 0] = int128_gethi(ov); @@ -1596,18 +1595,16 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, cpu_stq_data_ra(env, a2, svh, ra); break; case 4: - if (parallel) { -#ifdef CONFIG_ATOMIC128 + if (!parallel) { + cpu_stq_data_ra(env, a2 + 0, svh, ra); + cpu_stq_data_ra(env, a2 + 8, svl, ra); + } else if (HAVE_ATOMIC128) { TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 sv = int128_make128(svl, svh); helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); -#else + } else { /* Note that we asserted !parallel above. */ g_assert_not_reached(); -#endif - } else { - cpu_stq_data_ra(env, a2 + 0, svh, ra); - cpu_stq_data_ra(env, a2 + 8, svl, ra); } break; default: @@ -2105,21 +2102,18 @@ static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel) uintptr_t ra = GETPC(); uint64_t hi, lo; - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else + if (!parallel) { + check_alignment(env, addr, 16, ra); + hi = cpu_ldq_data_ra(env, addr + 0, ra); + lo = cpu_ldq_data_ra(env, addr + 8, ra); + } else if (HAVE_ATOMIC128) { int mem_idx = cpu_mmu_index(env, false); TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v = helper_atomic_ldo_be_mmu(env, addr, oi, ra); hi = int128_gethi(v); lo = int128_getlo(v); -#endif } else { - check_alignment(env, addr, 16, ra); - - hi = cpu_ldq_data_ra(env, addr + 0, ra); - lo = cpu_ldq_data_ra(env, addr + 8, ra); + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } env->retxl = lo; @@ -2142,21 +2136,17 @@ static void do_stpq(CPUS390XState *env, uint64_t addr, { uintptr_t ra = GETPC(); - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx = cpu_mmu_index(env, false); - TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - - Int128 v = int128_make128(low, high); - helper_atomic_sto_be_mmu(env, addr, v, oi, ra); -#endif - } else { + if (!parallel) { check_alignment(env, addr, 16, ra); - cpu_stq_data_ra(env, addr + 0, high, ra); cpu_stq_data_ra(env, addr + 8, low, ra); + } else if (HAVE_ATOMIC128) { + int mem_idx = cpu_mmu_index(env, false); + TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + Int128 v = int128_make128(low, high); + helper_atomic_sto_be_mmu(env, addr, v, oi, ra); + } else { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } }