From patchwork Mon Oct 8 21:21:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148456 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4141242lji; Mon, 8 Oct 2018 14:37:28 -0700 (PDT) X-Google-Smtp-Source: ACcGV639x1BUY94CObTzq6CWN5HEyvouQ/NYX+h1LdyzfHxHFYm8eq5ITeAvpt11nPeVBaJDO9+V X-Received: by 2002:a0c:c352:: with SMTP id j18-v6mr12393261qvi.38.1539034648471; Mon, 08 Oct 2018 14:37:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539034648; cv=none; d=google.com; s=arc-20160816; b=R7HoFVujaKBy/K9GUINaqFvh00ajvdKcqZTnV1TgEz0rq2krl4DlLE9GpG13JyffH8 9EqnSC8zMESeRhO0/PC5XnN7uvYBsV9r0nmFR4IItfZpxmatAEjKYozTOJE7JlMWx5pO lCEYbynwr9hrUPKvs0A02sV3zSYoiACopIf3vbKC0rKfItoaB+obOxxJ1NN8UmzPcQ5U F0sVHkfznYzxFjDsl5jxqs+m5z4lZVHE9Y26YjfbCci11GavDg16b6Y52k72WPM9Q3CG 6OIe2DSygL1rX/FrXL2tGfo+FzDsVtNaBsKpLCnzgSohqQRiK7YXaRBJHGr9LZuCjue6 iIKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=t5ntcVDQxgIMgTJgAEaytF6rOREVU67yK50aRSjbmKM=; b=KW6+/ld+GOBtyQo5s2AOBzCHykkQevy9JFqui1VacAkMcSd8Sayipfb+vpCCH0pWIK RsS7npoHqhY4hIhFay5eAm2xNbi2Qlj0DBp3X9mbQh+ss4mdX5Ql+seYVuuoexuyPGqY wzv/tP9krFuVwW7/pgrn+nzdnVg7k2WqSYvqDgJJzfdO7OIcBMEE6boTEIOG28mROfGl FdK8enKp2LlKWN+PHedtij2nLPkBRsZGy+eLZwncdG3Chp9MlbC8v9Fu7st5skEHj4mU ZmNASLQLWqPSJRR1qBVGj/Tnb0TOOWjkCF4UY0V2RnwKyRYvHSfNFdz1VuUKHUsloCFc plVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CeRGShbC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b12-v6si3978334qka.143.2018.10.08.14.37.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 08 Oct 2018 14:37:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CeRGShbC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48424 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9dDT-0003bd-TO for patch@linaro.org; Mon, 08 Oct 2018 17:37:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58538) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9d4T-0005Ft-Am for qemu-devel@nongnu.org; Mon, 08 Oct 2018 17:28:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9cyi-000866-Rs for qemu-devel@nongnu.org; Mon, 08 Oct 2018 17:22:16 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:34195) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g9cyi-00084z-E0 for qemu-devel@nongnu.org; Mon, 08 Oct 2018 17:22:12 -0400 Received: by mail-pl1-x62d.google.com with SMTP id f18-v6so10610954plr.1 for ; Mon, 08 Oct 2018 14:22:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t5ntcVDQxgIMgTJgAEaytF6rOREVU67yK50aRSjbmKM=; b=CeRGShbCEFg71yMZn3+1X1tFEuL5bW6OfPSPIFDELeUboeojhpXDJ3ER8aIITAPYTG 4rs12Gx2mYt2hMTBAbvsns4BDaN7XQdAC64v0mGfAAxhxqce6Dd5FtjI+CPzuC6qY+Ip tQLDT2rSRcwNFe8huA0y7td+3w52Z/Uu+0UB8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t5ntcVDQxgIMgTJgAEaytF6rOREVU67yK50aRSjbmKM=; b=Ke/Gd1BXK6wAumIVf50wU+KP16KqnRztKtCDFktqlbSzBKUsNQF2zcXPNuSHxyDDnM s+vlASmtPLpv3ziFxfrIGj9NGJmVdM+59w/xtch/vXFYi8bG9P8M0cggaFiLfu/Ale8U zAlun9v0Q2vuwF3wpxyFlMQSCkP1jN9LMniAHvJjKse4n+r1MpuuaCex7Bd3NlVafR/m kClhzG4bpYPQ8DaPEXkekEwL2hCqfNpIE8d2NwBOY8BHfZf2epSuaekipi38Z2ZPV1aj z69y21j8oNeIo8pNr/FhJXshizoJ6jbvMS7Mp9TTgoUUk29WK8Ej5BnuECLkvCwHVZEr 14cA== X-Gm-Message-State: ABuFfojEWeF+NYqUFP4zDmeoxf/Pqa+oBxlq/MasH1gvrHw8Ph7ggcOV 3TbVfzbOlXOtEW+P3pFrd06rYHMRu+c= X-Received: by 2002:a17:902:3324:: with SMTP id a33-v6mr25661544plc.208.1539033729872; Mon, 08 Oct 2018 14:22:09 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id r25-v6sm20392913pgm.59.2018.10.08.14.22.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 14:22:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 8 Oct 2018 14:21:56 -0700 Message-Id: <20181008212205.17752-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181008212205.17752-1-richard.henderson@linaro.org> References: <20181008212205.17752-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH v3 01/10] target/arm: Fix aarch64_sve_change_el wrt EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At present we assert: arm_el_is_aa64: Assertion `el >= 1 && el <= 3' failed. The comment in arm_el_is_aa64 explains why asking about EL0 without extra information is impossible. Add an extra argument to provide it from the surrounding context. Fixes: 0ab5953b00b3 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 +++++-- target/arm/helper.c | 16 ++++++++++++---- target/arm/op_helper.c | 6 +++++- 3 files changed, 22 insertions(+), 7 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3a2aff1192..54362ddce8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -911,10 +911,13 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el); +void aarch64_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64); #else static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } -static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n) { } +static inline void aarch64_sve_change_el(CPUARMState *env, int o, + int n, bool a) +{ } #endif target_ulong do_arm_semihosting(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index c83f7c1109..0efbb5c76c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8374,7 +8374,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) unsigned int new_mode = aarch64_pstate_mode(new_el, true); unsigned int cur_el = arm_current_el(env); - aarch64_sve_change_el(env, cur_el, new_el); + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); if (cur_el < new_el) { /* Entry vector offset depends on whether the implemented EL @@ -12791,9 +12795,11 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) /* * Notice a change in SVE vector size when changing EL. */ -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el) +void aarch64_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64) { int old_len, new_len; + bool old_a64, new_a64; /* Nothing to do if no SVE. */ if (!arm_feature(env, ARM_FEATURE_SVE)) { @@ -12817,9 +12823,11 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el) * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_len = (arm_el_is_aa64(env, old_el) && !sve_exception_el(env, old_el) + old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + old_len = (old_a64 && !sve_exception_el(env, old_el) ? sve_zcr_len_for_el(env, old_el) : 0); - new_len = (arm_el_is_aa64(env, new_el) && !sve_exception_el(env, new_el) + new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + new_len = (new_a64 && !sve_exception_el(env, new_el) ? sve_zcr_len_for_el(env, new_el) : 0); /* When changing vector length, clear inaccessible state. */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index fb15a13e6c..d915579712 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1101,7 +1101,11 @@ void HELPER(exception_return)(CPUARMState *env) "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } - aarch64_sve_change_el(env, cur_el, new_el); + /* + * Note that cur_el can never be 0. If new_el is 0, then + * el0_a64 is return_to_aa64, else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); qemu_mutex_lock_iothread(); arm_call_el_change_hook(arm_env_get_cpu(env));