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X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PULL 7/8] softfloat: Specialize udiv_qrnnd for s390x X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ISA has a 128/64-bit division instruction. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 39eb08b4f1..eafc68932b 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -641,6 +641,12 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, uint64_t q; asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d)); return q; +#elif defined(__s390x__) + /* Need to use a TImode type to get an even register pair for DLGR. */ + unsigned __int128 n = (unsigned __int128)n1 << 64 | n0; + asm("dlgr %0, %1" : "+r"(n) : "r"(d)); + *r = n >> 64; + return n; #else uint64_t d0, d1, q0, q1, r1, r0, m;