From patchwork Fri Oct 5 15:48:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 148200 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp617693lji; Fri, 5 Oct 2018 08:55:31 -0700 (PDT) X-Google-Smtp-Source: ACcGV60tHckxd4vTnsHcSHM0ufkLNlrKVaAntjPJl8Z+G5t3DDpj9aYy3iA+5TryEHUyZbxmoufE X-Received: by 2002:a37:bbc1:: with SMTP id l184-v6mr9747309qkf.111.1538754931314; Fri, 05 Oct 2018 08:55:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538754931; cv=none; d=google.com; s=arc-20160816; b=O4YsE87ujDH6N4iKJOEI3w7mQFPbwPox1ozW6dZ69tW2kcjh8bECydJfPO8Cp4TVE/ EyKjODg413qKxb+K8z5/Wm9KDUQW2sCjIsg8SdIerasFIIaE1ydAfdnW+/vVCDH+9JLG EkzK8sL2EiP0ONJrbJVbKrpt2XkQdF1fCk6dOcbXvC+UdiaovMqQqqxQnc1XU2JP2SG6 yTjekkDQnPw+r9sfLVyQK3lQOjlDH9mea1Yck55tomvlGwYnh+sqkc2z9K4zMz9zcTxt IiWh+cg6pSVfMMWRA+9/xUBqBGeHflwL3+oMaurFZNi49v4ruZHmK+oCj/XCVvLH/e8N P2XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=YMcYHFt4aPfyzdgpiXu+ijwKbSBzrDfmAxe8xFefia4=; b=egsY5MVRSEuWZMTZu0aQfBGh2x4OIZGAGvzknABkavS3gNP8WCYxKLq0zhdpFtZzea sjtpGBBHuymMvaSwIOrDQr3EPi4B/PI1MN43AcQhKgTFR17KSDjm7XHa38osGO0GC3NM itO/4eFoEjDJ64sxI3zvdhuBAhPprfYSnJ2nicA+nBOk2WUHvANNPIv2k4eYnYEg/9hs AZUX9zC1Gu0d83QqqoaqjW4QvjEk2y6QJ65KaosepjRtofrC+U4ML1YpE0hL5v0TVBxs pawOOLrfgDtnJlAS0tTT1pnWM0cw0rYfhNXNfZ6QDjIFbuAZVOvXKqgdtkuG09Z/ppNx +Ddw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eKhMWyRi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r2-v6si75511qvc.136.2018.10.05.08.55.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 05 Oct 2018 08:55:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eKhMWyRi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35729 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8SRu-0005bV-Og for patch@linaro.org; Fri, 05 Oct 2018 11:55:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56691) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8SM6-0006XU-St for qemu-devel@nongnu.org; Fri, 05 Oct 2018 11:49:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g8SM1-000667-Hp for qemu-devel@nongnu.org; Fri, 05 Oct 2018 11:49:29 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:43521) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g8SM0-00064G-MV for qemu-devel@nongnu.org; Fri, 05 Oct 2018 11:49:25 -0400 Received: by mail-wr1-x436.google.com with SMTP id n1-v6so14042960wrt.10 for ; Fri, 05 Oct 2018 08:49:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YMcYHFt4aPfyzdgpiXu+ijwKbSBzrDfmAxe8xFefia4=; b=eKhMWyRiLcRbYth9TNBLks3DT9TdXPh2Rm+XD438+P3Zd+p2kWGkH9VX+IW/cFXJuK kblD3hzdmiRKygJmsEJAcZGo4wUONwwijZMkektrAXVsjuJclDbMK3lV0hcIsnol7P35 xs7hyK080Km22RnEVKQb4yxsbLjeuo30eBsFs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YMcYHFt4aPfyzdgpiXu+ijwKbSBzrDfmAxe8xFefia4=; b=lBjiF0f01TuiLGA/BNkrn45QTFnIBSoVexAjHR++Ucke0f08NuLaBEzUuwdwsAAtpE hSXs/+p1+BZizciGE47q9xyd6V/ZM9Mn1FHe5KhnO65Rd0S4dfmS/uHGNsqVFGe04+DP s7wZmAxUzg1TAZXZAgFctsed8JgBZr//WOcjpOG4pPLYuW4U1/8Xm2eIPDfrtH8vS1yo VbUDwW5FzFvR6kuSeXBPD+hJWcPqayscrQ2KE9seiOVMlNX2gR2zFGKfsXPAoNwZa8oW CRaz2FcikkyEB5LRv+xm/QNob5CgcU1WzPkGru5lGWLPi//XU8xU7c+O0YXp5L37OxJW 3yBg== X-Gm-Message-State: ABuFfohA68qmAjvN/ZkcQo6DoCuDw7xy7V2/nzPRFi+ij3/8Jghe978L VWUYmf01DHouWm3xfUHmJVFNDA== X-Received: by 2002:a5d:618f:: with SMTP id j15-v6mr9459578wru.198.1538754559957; Fri, 05 Oct 2018 08:49:19 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y203-v6sm1499594wmd.1.2018.10.05.08.49.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Oct 2018 08:49:15 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 5B8B83E0632; Fri, 5 Oct 2018 16:49:11 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 5 Oct 2018 16:48:57 +0100 Message-Id: <20181005154910.3099-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005154910.3099-1-alex.bennee@linaro.org> References: <20181005154910.3099-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [RFC PATCH 08/21] accel/tcg/cputlb: convert remaining tlb_debug() to trace events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Crosthwaite , cota@braap.org, Pavel.Dovgaluk@ispras.ru, Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , vilanova@ac.upc.edu, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The last remaining user of tlb_debug() is the set page code. We can convert this to a trace event and remove associated logging machinery. The DEBUG_TLB define remains to enable self-check code when debugging. To avoid overly long lines in trace events I've split the event into tlb_set_page and tlb_set_page_attrs. Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 27 +++++---------------------- accel/tcg/trace-events | 5 +++++ 2 files changed, 10 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f1d4f7da44..abdc4c5d25 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -34,31 +34,16 @@ #include "exec/helper-proto.h" #include "qemu/atomic.h" -/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ +/* DEBUG_TLB turns on internal self-checks, actions are logged via + * trace-events */ /* #define DEBUG_TLB */ -/* #define DEBUG_TLB_LOG */ #ifdef DEBUG_TLB # define DEBUG_TLB_GATE 1 -# ifdef DEBUG_TLB_LOG -# define DEBUG_TLB_LOG_GATE 1 -# else -# define DEBUG_TLB_LOG_GATE 0 -# endif #else # define DEBUG_TLB_GATE 0 -# define DEBUG_TLB_LOG_GATE 0 #endif -#define tlb_debug(fmt, ...) do { \ - if (DEBUG_TLB_LOG_GATE) { \ - qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \ - ## __VA_ARGS__); \ - } else if (DEBUG_TLB_GATE) { \ - fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ - } \ -} while (0) - #define assert_cpu_is_self(this_cpu) do { \ if (DEBUG_TLB_GATE) { \ g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ @@ -124,7 +109,6 @@ static void tlb_flush_nocheck(CPUState *cpu) assert_cpu_is_self(cpu); atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); - tlb_debug("(count: %zu)\n", tlb_flush_count()); memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); @@ -629,6 +613,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, assert_cpu_is_self(cpu); + trace_tlb_set_page(cpu->cpu_index, vaddr, paddr); + trace_tlb_set_page_attrs(*(unsigned int *) &attrs, prot, mmu_idx, size); + if (size < TARGET_PAGE_SIZE) { sz = TARGET_PAGE_SIZE; } else { @@ -644,10 +631,6 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, &xlat, &sz, attrs, &prot); assert(sz >= TARGET_PAGE_SIZE); - tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx - " prot=%x idx=%d\n", - vaddr, paddr, prot, mmu_idx); - address = vaddr_page; if (size < TARGET_PAGE_SIZE) { /* diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events index 0d2b1c47ac..82705632f2 100644 --- a/accel/tcg/trace-events +++ b/accel/tcg/trace-events @@ -15,6 +15,11 @@ tlb_flush_synced_schedule(int line, int from, int to) "cputlb.c:%d from_cpu=%d t tlb_flush_all_work(int vcpu) "cpu %d" tlb_flush_work(int line, int vcpu, unsigned long data) "cputlb.c:%d cpu %d, %lux" tlb_flush_work_complete(int line, int vcpu) "cputlb.c:%d cpu %d" +# +# TLB entries +# +tlb_set_page(int vcpu, unsigned long vaddr, unsigned long paddr) "cpu:%d vaddr:0x%lx paddr:0x%lx" +tlb_set_page_attrs(unsigned int attrs, int prot, int mmu_idx, int size) "attrs:0x%x prot:0x%x mmu_idx:%d size:%d" # TCG related tracing (you still need -d nochain to get a full picture # as otherwise you'll only see the first TB executed in a chain)