| Message ID | 20180927211322.16118-7-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Rely on id regs instead of features | expand |
On 27/09/2018 23:13, Richard Henderson wrote: > Having V6 alone imply jazelle was wrong for cortex-m0. > Change to an assertion for V6 & !M. Correct. > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > target/arm/cpu.h | 6 +++++- > target/arm/translate.h | 1 + > target/arm/cpu.c | 17 ++++++++++++++--- > target/arm/translate.c | 2 +- > 4 files changed, 21 insertions(+), 5 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index cd57c5aae0..c9996d2534 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1557,7 +1557,6 @@ enum arm_features { > ARM_FEATURE_PMU, /* has PMU support */ > ARM_FEATURE_VBAR, /* has cp15 VBAR */ > ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ > - ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ > ARM_FEATURE_SVE, /* has Scalable Vector Extension */ > ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ > ARM_FEATURE_M_MAIN, /* M profile Main Extension */ > @@ -3119,6 +3118,11 @@ static inline bool aa32_feature_arm_div(ARMCPU *cpu) > return FIELD_EX32(cpu->id_isar0, ID_ISAR0, DIVIDE) > 1; > } > > +static inline bool aa32_feature_jazelle(ARMCPU *cpu) > +{ > + return FIELD_EX32(cpu->id_isar1, ID_ISAR1, JAZELLE) != 0; > +} > + > static inline bool aa32_feature_aes(ARMCPU *cpu) > { > return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) != 0; > diff --git a/target/arm/translate.h b/target/arm/translate.h > index 3eb863ae43..d8eafbe88d 100644 > --- a/target/arm/translate.h > +++ b/target/arm/translate.h > @@ -196,6 +196,7 @@ static inline TCGv_i32 get_ahp_flag(void) > > FORWARD_FEATURE(thumb_div) > FORWARD_FEATURE(arm_div) > +FORWARD_FEATURE(jazelle) > FORWARD_FEATURE(aes) > FORWARD_FEATURE(pmull) > FORWARD_FEATURE(sha1) > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 4f2372c6d7..41a1b27c61 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -850,8 +850,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > } > if (arm_feature(env, ARM_FEATURE_V6)) { > set_feature(env, ARM_FEATURE_V5); > - set_feature(env, ARM_FEATURE_JAZELLE); > if (!arm_feature(env, ARM_FEATURE_M)) { > + assert(aa32_feature_jazelle(cpu)); > set_feature(env, ARM_FEATURE_AUXCR); > } > } > @@ -1078,11 +1078,16 @@ static void arm926_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_VFP); > set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); > set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); > - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); > cpu->midr = 0x41069265; > cpu->reset_fpsid = 0x41011090; > cpu->ctr = 0x1dd20d2; > cpu->reset_sctlr = 0x00090078; > + > + /* > + * ARMv5 does not have the ID_ISAR registers, but we can still > + * set the field to indicate Jazelle support within QEMU. > + */ > + FIELD_DP32(cpu->id_isar1, ID_ISAR1, JAZELLE, 1); > } > > static void arm946_initfn(Object *obj) > @@ -1108,12 +1113,18 @@ static void arm1026_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_AUXCR); > set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); > set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); > - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); > cpu->midr = 0x4106a262; > cpu->reset_fpsid = 0x410110a0; > cpu->ctr = 0x1dd20d2; > cpu->reset_sctlr = 0x00090078; > cpu->reset_auxcr = 1; > + > + /* > + * ARMv5 does not have the ID_ISAR registers, but we can still > + * set the field to indicate Jazelle support within QEMU. > + */ > + FIELD_DP32(cpu->id_isar1, ID_ISAR1, JAZELLE, 1); > + > { > /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ > ARMCPRegInfo ifar = { > diff --git a/target/arm/translate.c b/target/arm/translate.c > index c94c69e331..4036be6828 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -42,7 +42,7 @@ > #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) > /* currently all emulated v5 cores are also v5TE, so don't bother */ > #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) > -#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE) > +#define ENABLE_ARCH_5J aa32_dc_feature_jazelle(s) > #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) > #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) > #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) >
On 27 September 2018 at 22:13, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Having V6 alone imply jazelle was wrong for cortex-m0.
True, but harmless, because the only place we tested the
ARM_FEATURE_JAZELLE was for the 'bxj' in disas_arm(), which
is unreachable for M-profile cores.
thanks
-- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cd57c5aae0..c9996d2534 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1557,7 +1557,6 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ @@ -3119,6 +3118,11 @@ static inline bool aa32_feature_arm_div(ARMCPU *cpu) return FIELD_EX32(cpu->id_isar0, ID_ISAR0, DIVIDE) > 1; } +static inline bool aa32_feature_jazelle(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar1, ID_ISAR1, JAZELLE) != 0; +} + static inline bool aa32_feature_aes(ARMCPU *cpu) { return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) != 0; diff --git a/target/arm/translate.h b/target/arm/translate.h index 3eb863ae43..d8eafbe88d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -196,6 +196,7 @@ static inline TCGv_i32 get_ahp_flag(void) FORWARD_FEATURE(thumb_div) FORWARD_FEATURE(arm_div) +FORWARD_FEATURE(jazelle) FORWARD_FEATURE(aes) FORWARD_FEATURE(pmull) FORWARD_FEATURE(sha1) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4f2372c6d7..41a1b27c61 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -850,8 +850,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_JAZELLE); if (!arm_feature(env, ARM_FEATURE_M)) { + assert(aa32_feature_jazelle(cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } @@ -1078,11 +1078,16 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr = 0x41069265; cpu->reset_fpsid = 0x41011090; cpu->ctr = 0x1dd20d2; cpu->reset_sctlr = 0x00090078; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + FIELD_DP32(cpu->id_isar1, ID_ISAR1, JAZELLE, 1); } static void arm946_initfn(Object *obj) @@ -1108,12 +1113,18 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr = 0x4106a262; cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; cpu->reset_sctlr = 0x00090078; cpu->reset_auxcr = 1; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + FIELD_DP32(cpu->id_isar1, ID_ISAR1, JAZELLE, 1); + { /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ ARMCPRegInfo ifar = { diff --git a/target/arm/translate.c b/target/arm/translate.c index c94c69e331..4036be6828 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -42,7 +42,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE) +#define ENABLE_ARCH_5J aa32_dc_feature_jazelle(s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
Having V6 alone imply jazelle was wrong for cortex-m0. Change to an assertion for V6 & !M. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 6 +++++- target/arm/translate.h | 1 + target/arm/cpu.c | 17 ++++++++++++++--- target/arm/translate.c | 2 +- 4 files changed, 21 insertions(+), 5 deletions(-) -- 2.17.1