[v2,1/9] target/arm: Define fields of ISAR registers

Message ID	20180927211322.16118-2-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:13:14 -0700 Message-Id: <20180927211322.16118-2-richard.henderson@linaro.org> In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org> References: <20180927211322.16118-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 1/9] target/arm: Define fields of ISAR registers Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Rely on id regs instead of features \| expand [v2,0/9] target/arm: Rely on id regs instead of features [v2,1/9] target/arm: Define fields of ISAR registers [v2,2/9] target/arm: Convert v8 extensions from feature bits to isar tests [v2,3/9] target/arm: Align cortex-r5 id_isar0 [v2,4/9] target/arm: Fix cortex-a7 id_isar0 [v2,5/9] target/arm: Convert division from feature bits to isar0 tests [v2,6/9] target/arm: Convert jazelle from feature bit to isar1 test [v2,7/9] target/arm: Convert t32ee from feature bit to isar3 test [v2,8/9] target/arm: Convert sve from feature bit to pfr0 test [v2,9/9] target/arm: Convert v8.2-fp16 from feature bit to pfr0 test

Message ID

20180927211322.16118-2-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu, 27 Sep 2018 14:13:14 -0700
Message-Id: <20180927211322.16118-2-richard.henderson@linaro.org>
In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org>
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Subject: [Qemu-devel] [PATCH v2 1/9] target/arm: Define fields of ISAR
	registers
Precedence: list
Cc: peter.maydell@linaro.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Rely on id regs instead of features | expand

Comments

Philippe Mathieu-Daudé Sept. 28, 2018, 1:53 p.m. UTC | #1

On 27/09/2018 23:13, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/cpu.h | 80 ++++++++++++++++++++++++++++++++++++++++++++++++

>  1 file changed, 80 insertions(+)

> 

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index 65c0fa0a65..e1b9270b8c 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -1428,6 +1428,86 @@ FIELD(V7M_CSSELR, LEVEL, 1, 3)

>   */

>  FIELD(V7M_CSSELR, INDEX, 0, 4)

>  

> +/*

> + * System register ID fields.

> + */

> +FIELD(ID_ISAR0, SWAP, 0, 4)

> +FIELD(ID_ISAR0, BITCOUNT, 4, 4)

> +FIELD(ID_ISAR0, BITFIELD, 8, 4)

> +FIELD(ID_ISAR0, CMPBRANCH, 12, 4)

> +FIELD(ID_ISAR0, COPROC, 16, 4)

> +FIELD(ID_ISAR0, DEBUG, 20, 4)

> +FIELD(ID_ISAR0, DIVIDE, 24, 4)

> +

> +FIELD(ID_ISAR1, ENDIAN, 0, 4)

> +FIELD(ID_ISAR1, EXCEPT, 4, 4)

> +FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)

> +FIELD(ID_ISAR1, EXTEND, 12, 4)

> +FIELD(ID_ISAR1, IFTHEN, 16, 4)

> +FIELD(ID_ISAR1, IMMEDIATE, 20, 4)

> +FIELD(ID_ISAR1, INTERWORK, 24, 4)

> +FIELD(ID_ISAR1, JAZELLE, 28, 4)

> +

> +FIELD(ID_ISAR2, LOADSTORE, 0, 4)

> +FIELD(ID_ISAR2, MEMHINT, 4, 4)

> +FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)

> +FIELD(ID_ISAR2, MULT, 12, 4)

> +FIELD(ID_ISAR2, MULTS, 16, 4)

> +FIELD(ID_ISAR2, MULTU, 20, 4)

> +FIELD(ID_ISAR2, PSR_AR, 24, 4)

> +FIELD(ID_ISAR2, REVERSAL, 28, 4)

> +

> +FIELD(ID_ISAR3, SATURATE, 0, 4)

> +FIELD(ID_ISAR3, SIMD, 4, 4)

> +FIELD(ID_ISAR3, SVC, 8, 4)

> +FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)

> +FIELD(ID_ISAR3, TABBRANCH, 16, 4)

> +FIELD(ID_ISAR3, T32COPY, 20, 4)

> +FIELD(ID_ISAR3, TRUENOP, 24, 4)

> +FIELD(ID_ISAR3, T32EE, 28, 4)

> +

> +FIELD(ID_ISAR4, UNPRIV, 0, 4)

> +FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)

> +FIELD(ID_ISAR4, WRITEBACK, 8, 4)

> +FIELD(ID_ISAR4, SMC, 12, 4)

> +FIELD(ID_ISAR4, BARRIER, 16, 4)

> +FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)

> +FIELD(ID_ISAR4, PSR_M, 24, 4)

> +FIELD(ID_ISAR4, SWP_FRAC, 28, 4)

> +

> +FIELD(ID_ISAR5, SEVL, 0, 4)

> +FIELD(ID_ISAR5, AES, 4, 4)

> +FIELD(ID_ISAR5, SHA1, 8, 4)

> +FIELD(ID_ISAR5, SHA2, 12, 4)

> +FIELD(ID_ISAR5, CRC32, 16, 4)

> +FIELD(ID_ISAR5, RDM, 24, 4)

> +FIELD(ID_ISAR5, VCMA, 28, 4)

> +

> +FIELD(ID_ISAR6, JSCVT, 0, 4)

> +FIELD(ID_ISAR6, DP, 4, 4)

> +FIELD(ID_ISAR6, FHM, 8, 4)


since v8.5:

   FIELD(ID_ISAR6, SB, 12, 4)
   FIELD(ID_ISAR6, SPECRES, 16, 4)

> +

> +FIELD(ID_AA64ISAR0, AES, 4, 4)

> +FIELD(ID_AA64ISAR0, SHA1, 8, 4)

> +FIELD(ID_AA64ISAR0, SHA2, 12, 4)

> +FIELD(ID_AA64ISAR0, CRC32, 16, 4)

> +FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)

> +FIELD(ID_AA64ISAR0, RDM, 28, 4)

> +FIELD(ID_AA64ISAR0, SHA3, 32, 4)

> +FIELD(ID_AA64ISAR0, SM3, 36, 4)

> +FIELD(ID_AA64ISAR0, SM4, 40, 4)

> +FIELD(ID_AA64ISAR0, DP, 44, 4)

> +FIELD(ID_AA64ISAR0, FHM, 48, 4)

since v8.4:

   FIELD(ID_AA64ISAR0, TS, 52, 4)

> +

> +FIELD(ID_AA64ISAR1, DPB, 0, 4)

> +FIELD(ID_AA64ISAR1, APA, 4, 4)

> +FIELD(ID_AA64ISAR1, API, 8, 4)

> +FIELD(ID_AA64ISAR1, JSCVT, 12, 4)

> +FIELD(ID_AA64ISAR1, FCMA, 16, 4)

> +FIELD(ID_AA64ISAR1, LRCPC, 20, 4)

> +FIELD(ID_AA64ISAR1, GPA, 24, 4)

> +FIELD(ID_AA64ISAR1, GPI, 28, 4)


since v8.5:

   FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
   FIELD(ID_AA64ISAR1, SB, 36, 4)
   FIELD(ID_AA64ISAR1, SPECRES, 40, 4)

> +

>  QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);

>  

>  /* If adding a feature bit which corresponds to a Linux ELF

> 


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 65c0fa0a65..e1b9270b8c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1428,6 +1428,86 @@  FIELD(V7M_CSSELR, LEVEL, 1, 3)
  */
 FIELD(V7M_CSSELR, INDEX, 0, 4)
 
+/*
+ * System register ID fields.
+ */
+FIELD(ID_ISAR0, SWAP, 0, 4)
+FIELD(ID_ISAR0, BITCOUNT, 4, 4)
+FIELD(ID_ISAR0, BITFIELD, 8, 4)
+FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
+FIELD(ID_ISAR0, COPROC, 16, 4)
+FIELD(ID_ISAR0, DEBUG, 20, 4)
+FIELD(ID_ISAR0, DIVIDE, 24, 4)
+
+FIELD(ID_ISAR1, ENDIAN, 0, 4)
+FIELD(ID_ISAR1, EXCEPT, 4, 4)
+FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
+FIELD(ID_ISAR1, EXTEND, 12, 4)
+FIELD(ID_ISAR1, IFTHEN, 16, 4)
+FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
+FIELD(ID_ISAR1, INTERWORK, 24, 4)
+FIELD(ID_ISAR1, JAZELLE, 28, 4)
+
+FIELD(ID_ISAR2, LOADSTORE, 0, 4)
+FIELD(ID_ISAR2, MEMHINT, 4, 4)
+FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
+FIELD(ID_ISAR2, MULT, 12, 4)
+FIELD(ID_ISAR2, MULTS, 16, 4)
+FIELD(ID_ISAR2, MULTU, 20, 4)
+FIELD(ID_ISAR2, PSR_AR, 24, 4)
+FIELD(ID_ISAR2, REVERSAL, 28, 4)
+
+FIELD(ID_ISAR3, SATURATE, 0, 4)
+FIELD(ID_ISAR3, SIMD, 4, 4)
+FIELD(ID_ISAR3, SVC, 8, 4)
+FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
+FIELD(ID_ISAR3, TABBRANCH, 16, 4)
+FIELD(ID_ISAR3, T32COPY, 20, 4)
+FIELD(ID_ISAR3, TRUENOP, 24, 4)
+FIELD(ID_ISAR3, T32EE, 28, 4)
+
+FIELD(ID_ISAR4, UNPRIV, 0, 4)
+FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
+FIELD(ID_ISAR4, WRITEBACK, 8, 4)
+FIELD(ID_ISAR4, SMC, 12, 4)
+FIELD(ID_ISAR4, BARRIER, 16, 4)
+FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
+FIELD(ID_ISAR4, PSR_M, 24, 4)
+FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
+
+FIELD(ID_ISAR5, SEVL, 0, 4)
+FIELD(ID_ISAR5, AES, 4, 4)
+FIELD(ID_ISAR5, SHA1, 8, 4)
+FIELD(ID_ISAR5, SHA2, 12, 4)
+FIELD(ID_ISAR5, CRC32, 16, 4)
+FIELD(ID_ISAR5, RDM, 24, 4)
+FIELD(ID_ISAR5, VCMA, 28, 4)
+
+FIELD(ID_ISAR6, JSCVT, 0, 4)
+FIELD(ID_ISAR6, DP, 4, 4)
+FIELD(ID_ISAR6, FHM, 8, 4)
+
+FIELD(ID_AA64ISAR0, AES, 4, 4)
+FIELD(ID_AA64ISAR0, SHA1, 8, 4)
+FIELD(ID_AA64ISAR0, SHA2, 12, 4)
+FIELD(ID_AA64ISAR0, CRC32, 16, 4)
+FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
+FIELD(ID_AA64ISAR0, RDM, 28, 4)
+FIELD(ID_AA64ISAR0, SHA3, 32, 4)
+FIELD(ID_AA64ISAR0, SM3, 36, 4)
+FIELD(ID_AA64ISAR0, SM4, 40, 4)
+FIELD(ID_AA64ISAR0, DP, 44, 4)
+FIELD(ID_AA64ISAR0, FHM, 48, 4)
+
+FIELD(ID_AA64ISAR1, DPB, 0, 4)
+FIELD(ID_AA64ISAR1, APA, 4, 4)
+FIELD(ID_AA64ISAR1, API, 8, 4)
+FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
+FIELD(ID_AA64ISAR1, FCMA, 16, 4)
+FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
+FIELD(ID_AA64ISAR1, GPA, 24, 4)
+FIELD(ID_AA64ISAR1, GPI, 28, 4)
+
 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
 
 /* If adding a feature bit which corresponds to a Linux ELF

[v2,1/9] target/arm: Define fields of ISAR registers

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