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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id k26-v6sm18648793pfb.167.2018.09.15.09.17.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Sep 2018 09:17:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 15 Sep 2018 09:17:29 -0700 Message-Id: <20180915161738.25257-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180915161738.25257-1-richard.henderson@linaro.org> References: <20180915161738.25257-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH 04/13] target/arm: Derive id_isar2 from features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? The assertion does fire for the old cpus; they may be existing bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a477e722af..379d6a08a4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -821,6 +821,40 @@ static uint32_t resolve_id_isar1(CPUARMState *env) return ret; } +static uint32_t resolve_id_isar2(CPUARMState *env, uint32_t orig) +{ + uint32_t ret = 0; + + /* LoadStore */ + ret = deposit32(ret, 0, 4, + arm_feature(env, ARM_FEATURE_V8) ? 2 : + arm_feature(env, ARM_FEATURE_V5) ? 1 : 0); + /* + * MemHint -- v7mp has pldw (4), v7 has pli (3), but values 1 & 2 + * mean the same thing, and there does not seem to be a way to tell + * them apart for v5 & v6. + */ + ret |= orig & MAKE_64BIT_MASK(4, 4); + /* MultiAccessInt -- micro-architectural detail. */ + ret |= orig & MAKE_64BIT_MASK(8, 4); + /* Mult -- note we don't support pre-armv4t. */ + ret = deposit32(ret, 12, 4, arm_feature(env, ARM_FEATURE_THUMB2) ? 2 : 1); + /* MultS -- note we don't support pre-armv4t. */ + ret = deposit32(ret, 16, 4, + arm_feature(env, ARM_FEATURE_V6) ? 3 : + arm_feature(env, ARM_FEATURE_V5) ? 2 : 1); + /* MultU -- note we don't support pre-armv4t. */ + ret = deposit32(ret, 20, 4, arm_feature(env, ARM_FEATURE_V6) ? 2 : 1); + /* PSR_AR */ + ret = deposit32(ret, 24, 4, arm_feature(env, ARM_FEATURE_M) ? 0 : 1); + /* Reversal */ + ret = deposit32(ret, 28, 4, + arm_feature(env, ARM_FEATURE_THUMB2) ? 2 : + arm_feature(env, ARM_FEATURE_V6) ? 1 : 0); + + return ret; +} + static void resolve_id_regs(ARMCPU *cpu) { CPUARMState *env = &cpu->env; @@ -833,6 +867,10 @@ static void resolve_id_regs(ARMCPU *cpu) orig = cpu->id_isar1; cpu->id_isar1 = resolve_id_isar1(env); g_assert_cmphex(cpu->id_isar1, ==, orig); + + orig = cpu->id_isar2; + cpu->id_isar2 = resolve_id_isar2(env, orig); + g_assert_cmphex(cpu->id_isar2, ==, orig); } static void arm_cpu_realizefn(DeviceState *dev, Error **errp)