From patchwork Tue Aug 21 04:33:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144676 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4790678ljj; Mon, 20 Aug 2018 21:44:56 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxKQA4Retm3EE+j70ZaZO9wJpgMiAcQgffw8MmgxboAz47e5YPB0poTrEV3GF/5QIgurnd9 X-Received: by 2002:a37:2c8:: with SMTP id v69-v6mr19432980qkg.413.1534826696523; Mon, 20 Aug 2018 21:44:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534826696; cv=none; d=google.com; s=arc-20160816; b=vPXHyOpwUNpCX7bF+oanGaWPVvP++WQPoqNhCodwuG7ea9A1i2LVkxMLIWTZS6JR3u BSjBVbxxnVFvY03pIzIo7ptIGZ6Yv8OUzQRKM49XbYelOCy52GgEjv/42LRpN51EgAUu vmIAkQXK2as9A9E63v7k0gP3U/4na44YMLjzpVBkH8yloxDtvrfK/ewW8f1ZfPmcLc8e eLIoivMH8ko9BSJVvlraQwWa1hv8yu7vq347U2H9365hJFKPtbOjuKlDs6+Mxixgwjsq RMBAIGCyJtchSTEQoreLVa7vI5iMlDyql3GHMGLBTFLJcCQKJpwrmSHtLO3z6/Ydu0lI P3Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=MBjNgDtFGDZkwA8z/vF6h2xBFNAUobuokCgu3Q+0r70=; b=njgngmKfXldvIM2GlHVvSxS5p/ejr3of0pwSUnMLQ5sgG3p+FoAH1zq/HIGSCB4iyD G1L05scGtPSeAwWtpOK2eK3cSi1Q8QiLiyBKOFD5MvxP+f+7jih9imaw9cv70cC9tTXp Ae9fAOmGx8VI5QKPQlmKbvwlE7D37vR07/GMBTR7eqMPw1NzLPSgCKcRtCvxi9irISoQ rZYPGCi1jWIG5ela0Dazegv2FZFeD5hw2iJT1QZV8xhVhmcgnfuNvwZ2bAq4q/tguOT8 fVzgOkuoxe5Ab0iIkZuKqaqLRhbAiRgUDi7pGAkdkJ974A/6s09A8AEeeI2ekV9onVmy PHkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=LmbYxYXh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w3-v6si782042qvw.271.2018.08.20.21.44.56 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:44:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=LmbYxYXh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50699 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryXH-0006M0-V6 for patch@linaro.org; Tue, 21 Aug 2018 00:44:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56520) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMt-0004C7-Tn for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMp-0000MW-03 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:11 -0400 Received: from ozlabs.org ([203.11.71.1]:39101) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMk-0000Gk-Ss; Tue, 21 Aug 2018 00:34:05 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9F4ql2z9sCh; Tue, 21 Aug 2018 14:33:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826033; bh=nvjBLhRZ4TSfC5LLasaHiomTJbRKh1sOGnFknL/Leqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LmbYxYXh7cnN0e7JbnhbY/ciVQnLmoeG/Z/5ZuRVJ1FQy8bFejq+vxWq3NKFBCKqu PLtt8bQbTjxxNO2jB6hgi7vEev7fqwRorwlhGKSFAdr6VPuSMCqwYAL0BHs8J9fWvS Njx1GtoivABIrTWfpKqGpYqgTk0VfrhvK5Kg0NRc= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:26 +1000 Message-Id: <20180821043343.7514-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 09/26] target/ppc: Use non-arithmetic conversions for fp load/store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Memory operations have no side effects on fp state. The use of a "real" conversions between float64 and float32 would raise exceptions for SNaN and out-of-range inputs. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 61 ++++++++++++++++++++++++------ target/ppc/helper.h | 4 +- target/ppc/translate/fp-impl.inc.c | 26 +++++-------- 3 files changed, 61 insertions(+), 30 deletions(-) -- 2.17.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 5af5241ab0..b9bb1b856e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -47,24 +47,61 @@ static inline bool fp_exceptions_enabled(CPUPPCState *env) /*****************************************************************************/ /* Floating point operations helpers */ -uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg) + +/* + * This is the non-arithmatic conversion that happens e.g. on loads. + * In the Power ISA pseudocode, this is called DOUBLE. + */ +uint64_t helper_todouble(uint32_t arg) { - CPU_FloatU f; - CPU_DoubleU d; + uint32_t abs_arg = arg & 0x7fffffff; + uint64_t ret; - f.l = arg; - d.d = float32_to_float64(f.f, &env->fp_status); - return d.ll; + if (likely(abs_arg >= 0x00800000)) { + /* Normalized operand, or Inf, or NaN. */ + ret = (uint64_t)extract32(arg, 30, 2) << 62; + ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59; + ret |= (uint64_t)extract32(arg, 0, 30) << 29; + } else { + /* Zero or Denormalized operand. */ + ret = (uint64_t)extract32(arg, 31, 1) << 63; + if (unlikely(abs_arg != 0)) { + /* Denormalized operand. */ + int shift = clz32(abs_arg) - 9; + int exp = -126 - shift + 1023; + ret |= (uint64_t)exp << 52; + ret |= abs_arg << (shift + 29); + } + } + return ret; } -uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg) +/* + * This is the non-arithmatic conversion that happens e.g. on stores. + * In the Power ISA pseudocode, this is called SINGLE. + */ +uint32_t helper_tosingle(uint64_t arg) { - CPU_FloatU f; - CPU_DoubleU d; + int exp = extract64(arg, 52, 11); + uint32_t ret; - d.ll = arg; - f.f = float64_to_float32(d.d, &env->fp_status); - return f.l; + if (likely(exp > 896)) { + /* No denormalization required (includes Inf, NaN). */ + ret = extract64(arg, 62, 2) << 30; + ret |= extract64(arg, 29, 30); + } else { + /* Zero or Denormal result. If the exponent is in bounds for + * a single-precision denormal result, extract the proper bits. + * If the input is not zero, and the exponent is out of bounds, + * then the result is undefined; this underflows to zero. + */ + ret = extract64(arg, 63, 1) << 31; + if (unlikely(exp >= 874)) { + /* Denormal result. */ + ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp); + } + } + return ret; } static inline int ppc_float32_get_unbiased_exp(float32 f) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 7ed72c2337..ef64248bc4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -61,8 +61,8 @@ DEF_HELPER_2(compute_fprf_float64, void, env, i64) DEF_HELPER_3(store_fpscr, void, env, i64, i32) DEF_HELPER_2(fpscr_clrbit, void, env, i32) DEF_HELPER_2(fpscr_setbit, void, env, i32) -DEF_HELPER_2(float64_to_float32, i32, env, i64) -DEF_HELPER_2(float32_to_float64, i64, env, i32) +DEF_HELPER_FLAGS_1(todouble, TCG_CALL_NO_RWG_SE, i64, i32) +DEF_HELPER_FLAGS_1(tosingle, TCG_CALL_NO_RWG_SE, i32, i64) DEF_HELPER_4(fcmpo, void, env, i64, i64, i32) DEF_HELPER_4(fcmpu, void, env, i64, i64, i32) diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.inc.c index 2fbd4d4f38..a6f522b85c 100644 --- a/target/ppc/translate/fp-impl.inc.c +++ b/target/ppc/translate/fp-impl.inc.c @@ -660,15 +660,12 @@ GEN_LDUF(name, ldop, op | 0x21, type); \ GEN_LDUXF(name, ldop, op | 0x01, type); \ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) -static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) { - TCGv t0 = tcg_temp_new(); - TCGv_i32 t1 = tcg_temp_new_i32(); - gen_qemu_ld32u(ctx, t0, arg2); - tcg_gen_trunc_tl_i32(t1, t0); - tcg_temp_free(t0); - gen_helper_float32_to_float64(arg1, cpu_env, t1); - tcg_temp_free_i32(t1); + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); + gen_helper_todouble(dest, tmp); + tcg_temp_free_i32(tmp); } /* lfd lfdu lfdux lfdx */ @@ -836,15 +833,12 @@ GEN_STUF(name, stop, op | 0x21, type); \ GEN_STUXF(name, stop, op | 0x01, type); \ GEN_STXF(name, stop, 0x17, op | 0x00, type) -static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr) { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv t1 = tcg_temp_new(); - gen_helper_float64_to_float32(t0, cpu_env, arg1); - tcg_gen_extu_i32_tl(t1, t0); - tcg_temp_free_i32(t0); - gen_qemu_st32(ctx, t1, arg2); - tcg_temp_free(t1); + TCGv_i32 tmp = tcg_temp_new_i32(); + gen_helper_tosingle(tmp, src); + tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); + tcg_temp_free_i32(tmp); } /* stfd stfdu stfdux stfdx */