| Message ID | 20180810193129.1556-6-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: More sve-ish fixes | expand |
On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson <richard.henderson@linaro.org> wrote: > These insns require u=1; failed to include that in the switch > cases. This probably happened during one of the rebases just > before final commit. > > Fixes: d17b7cdcf4e > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Laurent > --- > target/arm/translate-a64.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 4a0ca8c906..8a24278d79 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -11427,12 +11427,12 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) > } > feature = ARM_FEATURE_V8_DOTPROD; > break; > - case 0x8: /* FCMLA, #0 */ > - case 0x9: /* FCMLA, #90 */ > - case 0xa: /* FCMLA, #180 */ > - case 0xb: /* FCMLA, #270 */ > - case 0xc: /* FCADD, #90 */ > - case 0xe: /* FCADD, #270 */ > + case 0x18: /* FCMLA, #0 */ > + case 0x19: /* FCMLA, #90 */ > + case 0x1a: /* FCMLA, #180 */ > + case 0x1b: /* FCMLA, #270 */ > + case 0x1c: /* FCADD, #90 */ > + case 0x1e: /* FCADD, #270 */ > if (size == 0 > || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) > || (size == 3 && !is_q)) { > -- > 2.17.1 >
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4a0ca8c906..8a24278d79 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11427,12 +11427,12 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } feature = ARM_FEATURE_V8_DOTPROD; break; - case 0x8: /* FCMLA, #0 */ - case 0x9: /* FCMLA, #90 */ - case 0xa: /* FCMLA, #180 */ - case 0xb: /* FCMLA, #270 */ - case 0xc: /* FCADD, #90 */ - case 0xe: /* FCADD, #270 */ + case 0x18: /* FCMLA, #0 */ + case 0x19: /* FCMLA, #90 */ + case 0x1a: /* FCMLA, #180 */ + case 0x1b: /* FCMLA, #270 */ + case 0x1c: /* FCADD, #90 */ + case 0x1e: /* FCADD, #270 */ if (size == 0 || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) || (size == 3 && !is_q)) {
These insns require u=1; failed to include that in the switch cases. This probably happened during one of the rebases just before final commit. Fixes: d17b7cdcf4e Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-a64.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.17.1