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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id g28-v6sm20500949pfe.41.2018.08.10.12.31.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 10 Aug 2018 12:31:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 10 Aug 2018 12:31:24 -0700 Message-Id: <20180810193129.1556-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180810193129.1556-1-richard.henderson@linaro.org> References: <20180810193129.1556-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 1/6] target/arm: Adjust FPCR_MASK for FZ16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When support for FZ16 was added, we failed to include the bit within FPCR_MASK, which means that it could never be set. Continue to zero FZ16 when ARMv8.2-FP16 is not enabled. Fixes: d81ce0ef2c4 Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) -- 2.17.1 Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 33d06f2340..0176716a70 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1279,7 +1279,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); * we store the underlying state in fpscr and just mask on read/write. */ #define FPSR_MASK 0xf800009f -#define FPCR_MASK 0x07f79f00 +#define FPCR_MASK 0x07ff9f00 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 64ff71b722..452d5e182a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11351,6 +11351,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) int i; uint32_t changed; + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ + if (!arm_feature(env, ARM_FEATURE_V8_FP16)) { + val &= ~FPCR_FZ16; + } + changed = env->vfp.xregs[ARM_VFP_FPSCR]; env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); env->vfp.vec_len = (val >> 16) & 7;