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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id h57-v6si2219440qth.279.2018.07.23.15.01.09 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 23 Jul 2018 15:01:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Tf55B4gz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37037 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhitA-0005Gr-Um for patch@linaro.org; Mon, 23 Jul 2018 18:01:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40019) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhisy-0005Gb-1W for qemu-devel@nongnu.org; Mon, 23 Jul 2018 18:00:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fhisw-00080S-PY for qemu-devel@nongnu.org; Mon, 23 Jul 2018 18:00:56 -0400 Received: from mail-pl0-x241.google.com ([2607:f8b0:400e:c01::241]:34622) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fhisw-00080E-FR for qemu-devel@nongnu.org; Mon, 23 Jul 2018 18:00:54 -0400 Received: by mail-pl0-x241.google.com with SMTP id f6-v6so795005plo.1 for ; Mon, 23 Jul 2018 15:00:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=+5okS6sBEXmJQgxbM1qhQi64YkLT8QsrVa0oc+MT2Qc=; b=Tf55B4gz4kgr0VhD223vUtkcbswWRZhRMMtLo8rARgiHrdpQerI+e73ISpLURMgLEV geZQTC6JGHkzbIw+UF7UG13O88oh6C5uslZatgz3USM3PqojkbhwcO+r6r7VJeJPH28Q a7Ywa/8u8PSLY2fvokGZjR8wF5+i0KI9DM+W8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+5okS6sBEXmJQgxbM1qhQi64YkLT8QsrVa0oc+MT2Qc=; b=RttYvvna9wpQz0s/MKKmjrj/bXVQgJm3TyYqyBqbBqwwcIsfy0MSDI9RIintCk3WcV DO1eUhLzLQU1rcz3oe0wkNnM4QhoIQ44MGEvQXnocvtQJKznLJXVOXTlGHkydxK4/OkV SgNJjJpy7719fZoOhfv94y6lxKC8WhCCC/bQw7gcCGvdPI87XVozQts+GZmTN6nt/5kw wxUxi7YK9RV1nMn04mw2xYRa+qeQacmx68QUh1FVALEUPCvbqCuOHs/+4JzVrZxcZ5W3 qyoFsQv0GtvT2QTPotyneEsBd8FUS5zhSh+kRBFSEipISxj8PinV0O1Imb0WlZf24/+h q+5Q== X-Gm-Message-State: AOUpUlHzAjThl+ZXD/Qf8P6vNT6A6d1IpGH75aQmc1ruGyIflLELfyPE Q/bXZ0+QgTODL1sZPT61FTBumJOPZBA= X-Received: by 2002:a17:902:5a08:: with SMTP id q8-v6mr14254330pli.300.1532383251532; Mon, 23 Jul 2018 15:00:51 -0700 (PDT) Received: from cloudburst.twiddle.net.net ([2603:3004:4:2500::544c]) by smtp.gmail.com with ESMTPSA id d22-v6sm16515631pfk.69.2018.07.23.15.00.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 15:00:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:00:47 -0700 Message-Id: <20180723220047.31594-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH for-3.0?] target/arm: Add sve-max-vq cpu property to -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, armbru@redhat.com, mdroth@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows the default (and maximum) vector length to be set from the command-line. Which is extraordinarily helpful in debuging problems depending on vector length without having to bake knowledge of PR_SET_SVE_VL into every guest binary. Signed-off-by: Richard Henderson --- The argument for inclding this in 3.0 is that there appear to be several groups experimenting with SVE and using fixed vector lengths. While this is oddly against the design of SVE, it's probably going to keep happening. Plus, the wildly useful debugging aspect. I'm not 100% sure I've tickled all of the qapi parts in the proper order, but it appears to work ok: $ cat ~/z.c #include int main() { int i; asm("rdvl %0, 1" : "=r"(i)); printf("%d\n", i); return 0; } $ ./aarch64-linux-user/qemu-aarch64 ~/a.out 256 $ ./aarch64-linux-user/qemu-aarch64 -cpu max,sve-max-vq=1 ~/a.out 16 $ ./aarch64-linux-user/qemu-aarch64 -cpu max,sve-max-vq=8 ~/a.out 128 $ ./aarch64-linux-user/qemu-aarch64 -cpu max,sve-max-vq=33 ~/a.out can't apply global max-arm-cpu.sve-max-vq=33: unsupported SVE vector length Valid sve-max-vq in range [1-16] $ ./aarch64-linux-user/qemu-aarch64 -cpu max,sve-max-vq=-1 ~/a.out can't apply global max-arm-cpu.sve-max-vq=-1: Parameter 'sve-max-vq' expects uint32_t r~ --- target/arm/cpu.h | 3 +++ linux-user/syscall.c | 19 +++++++++++++------ target/arm/cpu.c | 6 +++--- target/arm/cpu64.c | 29 +++++++++++++++++++++++++++++ target/arm/helper.c | 7 +++++-- 5 files changed, 53 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e310ffc29d..9526ed27cb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -857,6 +857,9 @@ struct ARMCPU { /* Used to synchronize KVM and QEMU in-kernel device levels */ uint8_t device_irq_level; + + /* Used to set the maximum vector length the cpu will support. */ + uint32_t sve_max_vq; }; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index dfc851cc35..5a4af76c03 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10848,15 +10848,22 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, #endif #ifdef TARGET_AARCH64 case TARGET_PR_SVE_SET_VL: - /* We cannot support either PR_SVE_SET_VL_ONEXEC - or PR_SVE_VL_INHERIT. Therefore, anything above - ARM_MAX_VQ results in EINVAL. */ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or + * PR_SVE_VL_INHERIT. Note the kernel definition + * of sve_vl_valid allows for VQ=512, i.e. VL=8192, + * even though the current architectural maximum is VQ=16. + */ ret = -TARGET_EINVAL; if (arm_feature(cpu_env, ARM_FEATURE_SVE) - && arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) { + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { CPUARMState *env = cpu_env; - int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; - int vq = MAX(arg2 / 16, 1); + ARMCPU *cpu = arm_env_get_cpu(env); + uint32_t vq, old_vq; + + old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, cpu->sve_max_vq); if (vq < old_vq) { aarch64_sve_narrow_vq(env, vq); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 64a8005a4b..b25898ed4c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -168,9 +168,9 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |= CPTR_EZ; /* with maximum vector length */ - env->vfp.zcr_el[1] = ARM_MAX_VQ - 1; - env->vfp.zcr_el[2] = ARM_MAX_VQ - 1; - env->vfp.zcr_el[3] = ARM_MAX_VQ - 1; + env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; + env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; + env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d0581d59d8..800bff780e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,7 @@ #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "qapi/visitor.h" static inline void set_feature(CPUARMState *env, int feature) { @@ -217,6 +218,29 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + visit_type_uint32(v, name, &cpu->sve_max_vq, errp); +} + +static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + Error *err = NULL; + + visit_type_uint32(v, name, &cpu->sve_max_vq, &err); + + if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) { + error_setg(&err, "unsupported SVE vector length"); + error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n", + ARM_MAX_VQ); + } + error_propagate(errp, err); +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -253,6 +277,10 @@ static void aarch64_max_initfn(Object *obj) cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ #endif + + cpu->sve_max_vq = ARM_MAX_VQ; + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, + cpu_max_set_sve_vq, NULL, NULL, &error_fatal); } } @@ -405,6 +433,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) uint64_t pmask; assert(vq >= 1 && vq <= ARM_MAX_VQ); + assert(vq <= arm_env_get_cpu(env)->sve_max_vq); /* Zap the high bits of the zregs. */ for (i = 0; i < 32; i++) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 22d812240a..bc274bb6e7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12414,9 +12414,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, zcr_len = 0; } else { int current_el = arm_current_el(env); + ARMCPU *cpu = arm_env_get_cpu(env); - zcr_len = env->vfp.zcr_el[current_el <= 1 ? 1 : current_el]; - zcr_len &= 0xf; + zcr_len = cpu->sve_max_vq - 1; + if (current_el <= 1) { + zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + } if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); }