From patchwork Mon Jul 2 13:57:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 140763 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1965ljj; Mon, 2 Jul 2018 07:11:28 -0700 (PDT) X-Google-Smtp-Source: AAOMgpf3zfrYhSlZVvCW8jgsJzZ76SommrBb4xiVEBKE3iX3c74M70XWqFzPaw5scewehFwfML1C X-Received: by 2002:ac8:3835:: with SMTP id q50-v6mr22816340qtb.235.1530540688563; Mon, 02 Jul 2018 07:11:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530540688; cv=none; d=google.com; s=arc-20160816; b=buBel/MvaMv3l4YTNOoifmhN+mOt5QWP4CIctY8kPorXxvqZRbBasAimIU8dnv0J3r bLfs21VrxZVe9NzSDVXGvUUq5HCdnUU3uCDHPfyLAiye+Fa4Y7ghaPAgnUkgW0fk2NKs MMZ+JmcA/9dMCyVAAeCrY3D5dg9/y8+AimJLX3GZEa2oy2RPgWpCCvhomD9cJILpM0HZ r3690va/a+P48mmywqI8Nukm5O+vQl9kI6SGH2zj/4Ze8twLW9Gfxj/LQsbQoNv8/lb2 j7UwwMXBblJjiOsoSpikFsNLjLci/lLSSUzWCgE3qT3oDTSZJOIuUfiW1D5iE5cwdzI5 zDQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=XP26Su5f4Z0Z60ApQh47OEXkTrqSOl00r2acJz/P8YI=; b=h9vHINfxwQ2UoyI/XcwyZiwIMZ5twzFk5GHk/YAxlizXCXeQAv0hayWQ2OLWqgi+OZ cNtMkHR6fhnQmvlGNKGdZ8BjWqPVzTFr/+xU1YlHZse4jud3acRmiY1yl/nIlxdQW2BR KWtciB3fCcjQme7cf96hsvhobzZchkAg0BmOenyS6FQhWwlolan3QrregbHl3aCK+1IG ePoYcTywNhEKdK1YfUJs1z3uV5ywbpBSlgLnPPcPEBxSQT1DOQ9nNKe+G37k3f2JQGxp Y0/CMsb4mvmSAfWaMk1GuxM74lYAbTvztkF+bTxA8dNE2D469M6epe17LWnJMESbjZz7 uATA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b="o3RJ/vi8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h39-v6si4452885qth.227.2018.07.02.07.11.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 07:11:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b="o3RJ/vi8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from localhost ([::1]:33013 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZzY7-0003CY-SA for patch@linaro.org; Mon, 02 Jul 2018 10:11:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fZzLx-0002bY-Ah for qemu-devel@nongnu.org; Mon, 02 Jul 2018 09:58:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fZzLv-0008Gj-Bg for qemu-devel@nongnu.org; Mon, 02 Jul 2018 09:58:53 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:42723) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fZzLv-0008FG-2P for qemu-devel@nongnu.org; Mon, 02 Jul 2018 09:58:51 -0400 Received: by mail-pf0-x229.google.com with SMTP id v9-v6so6438010pff.9 for ; Mon, 02 Jul 2018 06:58:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XP26Su5f4Z0Z60ApQh47OEXkTrqSOl00r2acJz/P8YI=; b=o3RJ/vi8G7Gs9NsF5GMbLhNdsXmMjqKLsmkKri0F5uF8a5JAQKLdd38rqSaqOhTyqp baW6Jhfd94wYlVIXBLRWGskM28dHJyxKip4TjWXaGu/HQtXelEkauAwGAS95XxKEF5vz c9EmLaXGbtR4NKOLLJ+vf8b2BylmPz2Ghz1uIMEXtWdnDIv4QlVWNjpUVc9W8HNiQ/JP zfRvVGUCsuBgRwK3oIs/98kGSkCYx3MpGqMmxWfk3v043A5JqG0KjT1QdtFvGX1Emzi1 Xzh1+xecBWjrIgwpKm3Qlvzz0jDnrV4/1/Z5OxpSXizKZueWOJqpcY0xs8wmt+AV2voA K/Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XP26Su5f4Z0Z60ApQh47OEXkTrqSOl00r2acJz/P8YI=; b=DiiWfzuYWokG1aMpK3ujTeckVKaEzWNNELHpBylvinIFvuuv2ZRqwxc8dNzk1VvgBO jnzyNTcTDM++Sg3uAAKcAf/hqe7knEUCKGfVqDP0TQpoYb4AgB5J70lZ4oJCmsUmZ+2J vfleLdYEkAqf4V01kFB8kzuUNyBUDaiXGTplLQfVSi1nG96yGCLWSK9mhhYg/zagNl34 rRQF5eFhgKyEZkTYY1DQGM4e9npVPslWWOdmHvoICek9CoKDeZMPQfvVuLaHBIuDItYt Pfmn8itGqTvVrHV5T+OEMZ1L3HrqDownPCO1TOqO+rJVyQpGMmq2WukMdwXtOxYs5bN6 5Jfw== X-Gm-Message-State: APt69E2lI5x38WDgrpn/6rKiiW8w/qYNaelX7VwhHNok505VkXp4QH1k FJf2hJvHzAnGO0rbKHDfbx4CJVgZ X-Received: by 2002:a62:6f86:: with SMTP id k128-v6mr25574870pfc.150.1530539930078; Mon, 02 Jul 2018 06:58:50 -0700 (PDT) Received: from localhost (g90.124-44-6.ppp.wakwak.ne.jp. [124.44.6.90]) by smtp.gmail.com with ESMTPSA id l85-v6sm31228880pfk.79.2018.07.02.06.58.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Jul 2018 06:58:49 -0700 (PDT) From: Stafford Horne To: Peter Maydell Date: Mon, 2 Jul 2018 22:57:56 +0900 Message-Id: <20180702135806.7087-16-shorne@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180702135806.7087-1-shorne@gmail.com> References: <20180702135806.7087-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PULL 15/25] target/openrisc: Fix tlb flushing in mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Richard Henderson , QEMU Development Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.17.0 diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 7f458b0d17..c9702cd26c 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -32,6 +32,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); + target_ulong mr; int idx; switch (spr) { @@ -85,12 +86,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); + mr = env->tlb.dtlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.dtlb[idx].mr = rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr = rb; @@ -102,14 +106,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; + case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); + mr = env->tlb.itlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.itlb[idx].mr = rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr = rb; @@ -121,6 +129,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ break; + case TO_SPR(5, 1): /* MACLO */ env->mac = deposit64(env->mac, 0, 32, rb); break;