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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:16 -0700 Message-Id: <20180628030330.15615-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A store to SR changes interrupt state, which should return to the main loop to recognize that state. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index db149986af..59605aacca 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -877,7 +877,22 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti = tcg_const_i32(a->k); + TCGv_i32 ti; + + /* For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp = DISAS_EXIT; + + ti = tcg_const_i32(a->k); gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); tcg_temp_free_i32(ti); }