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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 2/5] target/arm: relax permission checks for HWCAP_CPUID registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Although technically not visible to userspace the kernel does make them visible via trap and emulate. For user mode we can provide the value directly but we need to relax our permission checks to do this. Signed-off-by: Alex Bennée --- target/arm/helper.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 6e6b1762e8..9d81feb124 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5813,7 +5813,19 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state != ARM_CP_STATE_AA32) { int mask = 0; switch (r->opc1) { - case 0: case 1: case 2: + case 0: +#ifdef CONFIG_USER_ONLY + /* Some AArch64 CPU ID/feature are exported to userspace + * by the kernel (see HWCAP_CPUID) */ + if (r->opc0 == 3 && r->crn == 0 && + (r->crm == 0 || + (r->crm >= 4 && r->crm <= 7))) { + mask = PL0_R; + break; + } +#endif + /* fall-through */ + case 1: case 2: /* min_EL EL1 */ mask = PL1_RW; break;