From patchwork Wed Jun 13 01:56:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 138399 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp111141lji; Tue, 12 Jun 2018 19:16:43 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI5zIGavANcuIjLPsF+6qH23XLAu7ZAZ6EGKDkbTwvRx51kXpbqn34GTWY8Ema7CDrXLzJz X-Received: by 2002:ac8:1c6e:: with SMTP id j43-v6mr2958709qtk.218.1528856203042; Tue, 12 Jun 2018 19:16:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528856203; cv=none; d=google.com; s=arc-20160816; b=tjElCBa1I7qrVK1d1XiIhqpw1sYzg0oxyP02oETZMXLlDhgn+4tNrcdROjWUvb/cYD taW7silbZBiA18lupD4hQNlK2MMhWx55xdJyqA+QZ322NSeZ8hW4DZBCFJbyTTGBoMcb cKuxtsuWzSeFQnPaxON8H+E4ArZ6JX7FYVdbURXO5LXkfam0iHqWAarIuriaAW2/QJxa lOcJ+vBOFavHG0VyYxRSfZZPhpZOy+D24p6dz7p+iXip6KjPwTH2SZ0LHvIzVWadnreZ gyPmtmeHhAQtGKZPqNaWxjTXz8GxO7nH8Wl0t7rW/B76wHwupOglrjZYdn/RUmz/c39J MQ7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lP7pAHqSFNFh7l1XUm+Cdv4v7MFH6sGk56YYuuXMtLg=; b=g5GTTxSonNrN8/mbADjhjVrgXR63ZeTS4t1QCpTRJG3HCHYnoE6e4wp0ZV1gk3hMxj 3ZbvMOJGQICUzXq5/kFnavtskf5MmYwS+rh1VthH5oqya02uqW6IPCrdlRYOIvFVgWn1 +Hr0ub7kd5fgA7pMQDz6P4+ne7W8KcDY9uuNYdJl1W4+Ro6KWBrO9brrEl4CueT2MSiL R/xhOgcebMTyU/uxp7+/hASKwDi5GBt1tHER7vT9WF1aZdVg24yboqdJeU8c5+kIJgkt vk0FgltvM7uNzE29ifaM7dzVs4x6TY9yfvqjlZ9TkMKBduifuDUtzh50KzHefQV91ZyL MBoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YtqzpGOo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y15-v6si1658189qvb.188.2018.06.12.19.16.42 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 12 Jun 2018 19:16:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YtqzpGOo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59387 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSvL0-0001BS-Fv for patch@linaro.org; Tue, 12 Jun 2018 22:16:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44152) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fSv2Q-0002bq-Nh for qemu-devel@nongnu.org; Tue, 12 Jun 2018 21:57:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fSv2P-0006KQ-5s for qemu-devel@nongnu.org; Tue, 12 Jun 2018 21:57:30 -0400 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]:36070) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fSv2O-0006K4-Th for qemu-devel@nongnu.org; Tue, 12 Jun 2018 21:57:29 -0400 Received: by mail-pf0-x22d.google.com with SMTP id a12-v6so509873pfi.3 for ; Tue, 12 Jun 2018 18:57:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lP7pAHqSFNFh7l1XUm+Cdv4v7MFH6sGk56YYuuXMtLg=; b=YtqzpGOowbdRrPTEPOJjqIkLse8OyKZ1kMLlQW4sWlbNHvgRJlNovQZYPFd2GzvUhD 8vlPlo+5Bp9Nlex5Xq8rhj+G4k645iFSGjepDkr1/j31wwYhHYIDHGUJeAAhfKs/u8k+ UkRVmtjWMIwR/MDbIrPi4KrAaRAozqPeND/IY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lP7pAHqSFNFh7l1XUm+Cdv4v7MFH6sGk56YYuuXMtLg=; b=opByPBH65tV3cbxpbb3MSlr7Zk+b2lxN+jBh0g0awlfQC/nMuG1PQqcfxblwahXsJ4 CsY4nBlqwKth0+jcPkGH4pJzLGxBimjor8PB7gV0B/KxyJzJz0+6U50ilBEqhKgAB1ZU RIim6WSvAcIn7prWDcrs0htlhotgEKpqKC+ciM/Z4FwkoUTJCiEV5zLgx0OSC5yEf3vO VZiQMs8rjFfVbC5g/BoKl0wQzNAEugIm5Zo+njWv4KBX7C97fbfUFObvhjogkVqwONof mBTRyhXw238cznk5jo7dfry01SPIJOMDXShzcYRdZA/OIz9uvJnHvJhw6hmCdgqwAJvu AoHw== X-Gm-Message-State: APt69E1pgNMiDHzEV1mi7IErqia+IV+WqP4OJkHSDfRIqNaSIt1VCeAd E+BLMQzxnCoEBUR+uGHHqAc5d6V6v3k= X-Received: by 2002:a62:d913:: with SMTP id s19-v6mr2842502pfg.39.1528855047512; Tue, 12 Jun 2018 18:57:27 -0700 (PDT) Received: from cloudburst.twiddle.net (rrcs-173-198-77-219.west.biz.rr.com. [173.198.77.219]) by smtp.gmail.com with ESMTPSA id g10-v6sm1647287pfi.148.2018.06.12.18.57.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Jun 2018 18:57:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Jun 2018 15:56:38 -1000 Message-Id: <20180613015641.5667-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613015641.5667-1-richard.henderson@linaro.org> References: <20180613015641.5667-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PATCH v4b 15/18] target/arm: Implement SVE Integer Compare - Scalars Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 + target/arm/sve_helper.c | 31 ++++++++++++ target/arm/translate-sve.c | 99 ++++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 8 +++ 4 files changed, 140 insertions(+) -- 2.17.1 diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index dd4f8f754d..1863106d0f 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -678,3 +678,5 @@ DEF_HELPER_FLAGS_4(sve_brkn, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_cntp, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sve_while, TCG_CALL_NO_RWG, i32, ptr, i32, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index a4ecd653c1..8539595bd7 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2738,3 +2738,34 @@ uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc) } return sum; } + +uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc) +{ + uintptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; + intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); + uint64_t esz_mask = pred_esz_masks[esz]; + ARMPredicateReg *d = vd; + uint32_t flags; + intptr_t i; + + /* Begin with a zero predicate register. */ + flags = do_zero(d, oprsz); + if (count == 0) { + return flags; + } + + /* Scale from predicate element count to bits. */ + count <<= esz; + /* Bound to the bits in the predicate. */ + count = MIN(count, oprsz * 8); + + /* Set all of the requested bits. */ + for (i = 0; i < count / 64; ++i) { + d->p[i] = esz_mask; + } + if (count & 63) { + d->p[i] = MAKE_64BIT_MASK(0, count & 63) & esz_mask; + } + + return predtest_ones(d, oprsz, esz_mask); +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 6b0b8c55d0..ae6a504f61 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3092,6 +3092,105 @@ static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a, return true; } +/* + *** SVE Integer Compare Scalars Group + */ + +static bool trans_CTERM(DisasContext *s, arg_CTERM *a, uint32_t insn) +{ + if (!sve_access_check(s)) { + return true; + } + + TCGCond cond = (a->ne ? TCG_COND_NE : TCG_COND_EQ); + TCGv_i64 rn = read_cpu_reg(s, a->rn, a->sf); + TCGv_i64 rm = read_cpu_reg(s, a->rm, a->sf); + TCGv_i64 cmp = tcg_temp_new_i64(); + + tcg_gen_setcond_i64(cond, cmp, rn, rm); + tcg_gen_extrl_i64_i32(cpu_NF, cmp); + tcg_temp_free_i64(cmp); + + /* VF = !NF & !CF. */ + tcg_gen_xori_i32(cpu_VF, cpu_NF, 1); + tcg_gen_andc_i32(cpu_VF, cpu_VF, cpu_CF); + + /* Both NF and VF actually look at bit 31. */ + tcg_gen_neg_i32(cpu_NF, cpu_NF); + tcg_gen_neg_i32(cpu_VF, cpu_VF); + return true; +} + +static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn) +{ + if (!sve_access_check(s)) { + return true; + } + + TCGv_i64 op0 = read_cpu_reg(s, a->rn, 1); + TCGv_i64 op1 = read_cpu_reg(s, a->rm, 1); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i32 t2, t3; + TCGv_ptr ptr; + unsigned desc, vsz = vec_full_reg_size(s); + TCGCond cond; + + if (!a->sf) { + if (a->u) { + tcg_gen_ext32u_i64(op0, op0); + tcg_gen_ext32u_i64(op1, op1); + } else { + tcg_gen_ext32s_i64(op0, op0); + tcg_gen_ext32s_i64(op1, op1); + } + } + + /* For the helper, compress the different conditions into a computation + * of how many iterations for which the condition is true. + * + * This is slightly complicated by 0 <= UINT64_MAX, which is nominally + * 2**64 iterations, overflowing to 0. Of course, predicate registers + * aren't that large, so any value >= predicate size is sufficient. + */ + tcg_gen_sub_i64(t0, op1, op0); + + /* t0 = MIN(op1 - op0, vsz). */ + tcg_gen_movi_i64(t1, vsz); + tcg_gen_umin_i64(t0, t0, t1); + if (a->eq) { + /* Equality means one more iteration. */ + tcg_gen_addi_i64(t0, t0, 1); + } + + /* t0 = (condition true ? t0 : 0). */ + cond = (a->u + ? (a->eq ? TCG_COND_LEU : TCG_COND_LTU) + : (a->eq ? TCG_COND_LE : TCG_COND_LT)); + tcg_gen_movi_i64(t1, 0); + tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); + + t2 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t2, t0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + desc = (vsz / 8) - 2; + desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); + t3 = tcg_const_i32(desc); + + ptr = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); + + gen_helper_sve_while(t2, ptr, t2, t3); + do_pred_flags(t2); + + tcg_temp_free_ptr(ptr); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + return true; +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 62d51c252b..4b718060a9 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -606,6 +606,14 @@ SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred # SVE saturating inc/dec vector by predicate count SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred +### SVE Integer Compare - Scalars Group + +# SVE conditionally terminate scalars +CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 + +# SVE integer compare scalar count and limit +WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 + ### SVE Memory - 32-bit Gather and Unsized Contiguous Group # SVE load predicate register