| Message ID | 20180514221219.7091-7-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | softfloat patch roundup | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > fpu/softfloat-specialize.h | 15 +++++++++++++++ > fpu/softfloat.c | 12 ++---------- > 2 files changed, 17 insertions(+), 10 deletions(-) > > diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h > index 4fc9ea4ac0..515cb12cfa 100644 > --- a/fpu/softfloat-specialize.h > +++ b/fpu/softfloat-specialize.h > @@ -86,6 +86,21 @@ this code that are retained. > #define NO_SIGNALING_NANS 1 > #endif > > +/*---------------------------------------------------------------------------- > +| For the deconstructed floating-point with fraction FRAC, return true > +| if the fraction represents a signalling NaN; otherwise false. > +*----------------------------------------------------------------------------*/ > + > +static bool parts_is_snan_frac(uint64_t frac, float_status *status) > +{ > +#ifdef NO_SIGNALING_NANS > + return false; > +#else > + flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); > + return msb == status->snan_bit_is_one; > +#endif > +} > + > /*---------------------------------------------------------------------------- > | The pattern for a default generated half-precision NaN. > *----------------------------------------------------------------------------*/ > diff --git a/fpu/softfloat.c b/fpu/softfloat.c > index 607c4a78d5..19f40d6932 100644 > --- a/fpu/softfloat.c > +++ b/fpu/softfloat.c > @@ -331,16 +331,8 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, > part.cls = float_class_inf; > } else { > part.frac <<= parm->frac_shift; > -#ifdef NO_SIGNALING_NANS > - part.cls = float_class_qnan; > -#else > - int64_t msb = part.frac << 2; > - if ((msb < 0) == status->snan_bit_is_one) { > - part.cls = float_class_snan; > - } else { > - part.cls = float_class_qnan; > - } > -#endif > + part.cls = (parts_is_snan_frac(part.frac, status) > + ? float_class_snan : float_class_qnan); > } > } else if (part.exp == 0) { > if (likely(part.frac == 0)) { -- Alex Bennée
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 4fc9ea4ac0..515cb12cfa 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -86,6 +86,21 @@ this code that are retained. #define NO_SIGNALING_NANS 1 #endif +/*---------------------------------------------------------------------------- +| For the deconstructed floating-point with fraction FRAC, return true +| if the fraction represents a signalling NaN; otherwise false. +*----------------------------------------------------------------------------*/ + +static bool parts_is_snan_frac(uint64_t frac, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return false; +#else + flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); + return msb == status->snan_bit_is_one; +#endif +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 607c4a78d5..19f40d6932 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -331,16 +331,8 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, part.cls = float_class_inf; } else { part.frac <<= parm->frac_shift; -#ifdef NO_SIGNALING_NANS - part.cls = float_class_qnan; -#else - int64_t msb = part.frac << 2; - if ((msb < 0) == status->snan_bit_is_one) { - part.cls = float_class_snan; - } else { - part.cls = float_class_qnan; - } -#endif + part.cls = (parts_is_snan_frac(part.frac, status) + ? float_class_snan : float_class_qnan); } } else if (part.exp == 0) { if (likely(part.frac == 0)) {