From patchwork Mon May 14 22:12:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135772 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp194141lji; Mon, 14 May 2018 15:23:04 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo+Epw5745K/XQ0+JQ0LBLAEz6EmOjuHcG4jCNt9rIQWUFGZWFu/6X9CmC6OmYRBn2ka3ZX X-Received: by 2002:a37:7f46:: with SMTP id a67-v6mr5721693qkd.351.1526336584256; Mon, 14 May 2018 15:23:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526336584; cv=none; d=google.com; s=arc-20160816; b=QrR05YxObjoDDuo8bpPq/TvlkZEbY82R3n+0ARyLIhVj6AKg798gt9/NgU/0vWlduX vZSNfq8tNnBVSg70DfbLd1RSYnQzEXfwSB53nAzm7X4DAJW4A87hmQbw7aUxPdvb7dK7 QyTSHU70ptCj+3CyxM/rurdoI1sTXCW5GPrJXYuQaRPDGAIZTS96Otq6Z6DQqNS2WA1N o3qXMcPmN+c4IOMES/KoONJp3PFrSae8RprZPOrBIDr8tGc4vA5/AicYAwEq+XqZ9N0X K/u14YFG1ddH4Py05musa9dW5Tgj+CFeH+yoPD7rYzrBB9XadSagewLy+pO0zeXLHSww +Z+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xMM/6wnUJ8B/UfH6AgnsVWQZAYVhlZ+l678zaVK2h38=; b=lDMFZMdW0oAUpzBe85r7Ksb2XKD2i2vulNlxzMy5g00CiMcrw9f1Db9zm5pIUv1vEX CF4fN/nTNH3IT+6AVVr8AFcgfgs2tt64D93gIQjdY1jgtnY+H5DXE0PgOgxJqdQZ20S6 8xsvaqJ0vXBAnT1f8VOtqY+UBG0kNpo+rlHCofTkMLTqspYRxh6d/rG1K2mHTVwa/NgF b0+w67BGsgYXZa1yvB6CBSfKE/Ngc8rq6IyFRPspp4nOqQq6ppgDkx+/aR+tMV3bSQ5w /pAmrO83ohYTvFrTNUmV3SlXgXdKRLDd3ntWZA9ZM0bhL1PlKY3upzzrRZhEQCsLOp3B +7cQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RJOvV0rL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o15-v6si765384qvh.62.2018.05.14.15.23.04 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 14 May 2018 15:23:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RJOvV0rL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49940 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILrz-0008BA-Hr for patch@linaro.org; Mon, 14 May 2018 18:23:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fILhy-00081F-3a for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fILhw-0007sY-Uf for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:42 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:42032) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fILhw-0007qm-PE for qemu-devel@nongnu.org; Mon, 14 May 2018 18:12:40 -0400 Received: by mail-pg0-x242.google.com with SMTP id p9-v6so6060364pgc.9 for ; Mon, 14 May 2018 15:12:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xMM/6wnUJ8B/UfH6AgnsVWQZAYVhlZ+l678zaVK2h38=; b=RJOvV0rLN3a256X/U6her30qw+7VdMJZO6/23LTYn8zXILaytmUIlfCmkUxrF0S7Gb m4xPVrJvMtQLWCR/lnr6gm+3PUH1tPLwNbltdy4sCqye7ghZEi6U8Ykz4qyrcGJEsmFz I3QDflfnS6rgCu/+gsZw+izlNqjA+TRrqsaz4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xMM/6wnUJ8B/UfH6AgnsVWQZAYVhlZ+l678zaVK2h38=; b=FRWu2btsALyVCg8r5hGdEBl6YEfo8c0RyIZnS8jUTeqbQveULjgohci0OE75BXnW+H R79AITsEf3Q3SBQCDg+1iOpjZwNsOBoSwHNEJzVjyKQHeVvmLMBk/e+7tZUpMm/Jw8NX 1h3Yxf80GoZb8N6u0MVfNRG9YNVRQ4EEToPeaa8rBAdelXuLv7dpbTK764CbGXo2nEXO Ie6W6DOPWiAMNLalb88aUOqanlSxsgI/hzLqlpKNg7vTQn/kXPp9K6yQG51JLhAIfCvJ T3dQFjbKzL46v8kizlH/WDcjJhv6G7zr+/Lscf9T606hrhJX8zg/haiV/BYigWwoVmbh BUDg== X-Gm-Message-State: ALKqPwdUGTsgwS8KC/SNh5yjmHlk2JYqawmJ+Yo392phErEErOpXlblS xYjmB4xrLOv0EnHSv2z0lxAhnjCw4u0= X-Received: by 2002:a65:53ca:: with SMTP id z10-v6mr7726785pgr.413.1526335959580; Mon, 14 May 2018 15:12:39 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id y2-v6sm14512457pgp.92.2018.05.14.15.12.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 May 2018 15:12:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 May 2018 15:12:04 -0700 Message-Id: <20180514221219.7091-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180514221219.7091-1-richard.henderson@linaro.org> References: <20180514221219.7091-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v5 13/28] fpu/softfloat: Partial support for ARM Alternative half-precision X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée For float16 ARM supports an alternative half-precision format which sacrifices the ability to represent NaN/Inf in return for a higher dynamic range. The new FloatFmt flag, arm_althp, is then used to modify the behaviour of canonicalize and round_canonical with respect to representation and exception raising. Usage of this new flag waits until we re-factor float-to-float conversions. Signed-off-by: Alex Bennée Signed-off-by: Richard Henderson --- v3 - squash NaN to 0 if destination is AHP F16 v4 - handle inf -> ahp max in float_to_float not round_canonical - assert no nan and inf for ahp in round_canonical - check ahp before snan in float_to_float v5 - split out canonicalize and round_canonical changes from the rest --- fpu/softfloat.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) -- 2.17.0 Reviewed-by: Peter Maydell diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 41253c6749..55d0d01ec3 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -220,8 +220,10 @@ typedef struct { * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_POINT * The following are computed based the size of fraction * frac_lsb: least significant bit of fraction - * fram_lsbm1: the bit bellow the least significant bit (for rounding) + * frac_lsbm1: the bit bellow the least significant bit (for rounding) * round_mask/roundeven_mask: masks used for rounding + * The following optional modifiers are available: + * arm_althp: handle ARM Alternative Half Precision */ typedef struct { int exp_size; @@ -233,6 +235,7 @@ typedef struct { uint64_t frac_lsbm1; uint64_t round_mask; uint64_t roundeven_mask; + bool arm_althp; } FloatFmt; /* Expand fields based on the size of exponent and fraction */ @@ -324,7 +327,7 @@ static inline float64 float64_pack_raw(FloatParts p) static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, float_status *status) { - if (part.exp == parm->exp_max) { + if (part.exp == parm->exp_max && !parm->arm_althp) { if (part.frac == 0) { part.cls = float_class_inf; } else { @@ -413,7 +416,15 @@ static FloatParts round_canonical(FloatParts p, float_status *s, } frac >>= frac_shift; - if (unlikely(exp >= exp_max)) { + if (parm->arm_althp) { + /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ + if (unlikely(exp > exp_max)) { + /* Overflow. Return the maximum normal. */ + flags = float_flag_invalid; + exp = exp_max; + frac = -1; + } + } else if (unlikely(exp >= exp_max)) { flags |= float_flag_overflow | float_flag_inexact; if (overflow_norm) { exp = exp_max - 1; @@ -464,12 +475,14 @@ static FloatParts round_canonical(FloatParts p, float_status *s, case float_class_inf: do_inf: + assert(!parm->arm_althp); exp = exp_max; frac = 0; break; case float_class_qnan: case float_class_snan: + assert(!parm->arm_althp); exp = exp_max; frac >>= parm->frac_shift; break;