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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id 23-v6sm13270443pfs.147.2018.05.11.18.48.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 May 2018 18:48:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 11 May 2018 18:48:01 -0700 Message-Id: <20180512014801.17566-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512014801.17566-1-richard.henderson@linaro.org> References: <20180512014801.17566-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 2/2] target/s390x: Fix brace Werror with clang 6.0.0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cornelia Huck , Alexander Graf , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The warning is target/s390x/misc_helper.c:209:21: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] SysIB sysib = { 0 }; ^ {} While the original code is correct, and technically exactly correct as per ISO C89, both GCC and Clang support plain empty set of braces as an extension. Cc: Alexander Graf Cc: David Hildenbrand Cc: Cornelia Huck Signed-off-by: Richard Henderson --- target/s390x/misc_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index e0b23c1fd1..1f834f35ef 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -206,7 +206,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1) const MachineState *ms = MACHINE(qdev_get_machine()); uint16_t total_cpus = 0, conf_cpus = 0, reserved_cpus = 0; S390CPU *cpu = s390_env_get_cpu(env); - SysIB sysib = { 0 }; + SysIB sysib = { }; int i, cc = 0; if ((r0 & STSI_R0_FC_MASK) > STSI_R0_FC_LEVEL_3) {