From patchwork Fri May 11 04:23:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135495 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp394086lji; Thu, 10 May 2018 21:29:29 -0700 (PDT) X-Google-Smtp-Source: AB8JxZovnP3HM3uw8gFakCVqcuMqCflyFUyq0HZ/U2cd8GuAXo+FR1823J/RxC9YfuUYIdhB1la5 X-Received: by 2002:ac8:73c4:: with SMTP id v4-v6mr4064368qtp.115.1526012969050; Thu, 10 May 2018 21:29:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526012969; cv=none; d=google.com; s=arc-20160816; b=XnU5JZ5en4NPQ4J/xlfoQdrFO35XfQctMYFjFSTXWWhrui8WPFzj9tAKKQ3nNeoocV M/EoCMpmpdqhH+sSdwplwoDVMGYMPsgth4PI6r26dceKGjC9J6l0b+20WB/m59Dfe7nP 5XPwwCm04gClRGDXS8Bt3TgI980ZLwvJwyVD4lvw6w5bHyba9ALZFau04dA9dJRSZAHj 0lhLBFwDsALU/4wK7mEy2oaeEEzwOz9CGq3JNpC1d/lhPNiGmp2KAdAYibD4EgS3VknZ RPYHlJCDpX+OKdZ7dPfEXMICroQaTOcfoiqmjewQ0Ev92S4UQANLXo0wLAtwBKx3dSh/ CIIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=z7p2K9NKWam7z055uDI/yGQyctt6xvQmsMmSqbtcR4Q=; b=yDnr00HfO8EmPHzt6Dd+uvAK/D+2RTsiKc8JxD8wGgswQHuGOwmoTUUsnDTiZ+li0J MPiXjSdh4fUnkxAee3akD6vQk/95S5bJk1JKMzD+7ThYWv6KJpF1VM43yHMzyBDRvJez i2uVRnzsXYlW2IRoIRDX2mwW6Qg0FwTfLOXM8ND4jvz9dNtIqcO6y4N8KQnnHug9NGIM v7SakrpOJusDSY4f4EBdVMwLJcBuAG+HqMnfRbNfY4RlmGElMp/bYC6GJu+REnmCsEEJ JZtJQ6YA2Y8dv0CEvK2wvN1lQAOIEyVJhMKvluwQx9smxfAP3A7nRBmwyPaVd8jFzAgI 8SUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GIwd1VQN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 2-v6si2382059qku.200.2018.05.10.21.29.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 10 May 2018 21:29:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GIwd1VQN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36699 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGzgO-0007rm-Cj for patch@linaro.org; Fri, 11 May 2018 00:29:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGzae-0000Wz-Sg for qemu-devel@nongnu.org; Fri, 11 May 2018 00:23:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fGzac-00085H-61 for qemu-devel@nongnu.org; Fri, 11 May 2018 00:23:32 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:33239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fGzab-00085D-SJ for qemu-devel@nongnu.org; Fri, 11 May 2018 00:23:30 -0400 Received: by mail-pf0-x244.google.com with SMTP id f20-v6so2101705pfn.0 for ; Thu, 10 May 2018 21:23:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z7p2K9NKWam7z055uDI/yGQyctt6xvQmsMmSqbtcR4Q=; b=GIwd1VQN1EZBC1N8095JfG68tcdJnGtV0a0nN0nmWatl+VCeNr/WHfSl5mwOvA9TQ8 EokhhBY+9ImY6Ytbet8tUGeeYXjExBMwWezEcayHn5aiIXSMms5GVrJX+ggMCf6Zsjed lI9fXhhTDzPzq4PtKh7FHHGCAR6AK25Izkxfo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z7p2K9NKWam7z055uDI/yGQyctt6xvQmsMmSqbtcR4Q=; b=Dv9QptGLSBUgR/8aXVR8A+7Bh9KVe+mx14plbOJmPgMSroUBc3nXmUcAV5Jw5KE8wt KEShORm2k8ScRtIqJxaWnS4qW0ISlw7gLgk7JdxYpDw58XxnOUyO9fMUiOtA2mp1ml+C TEjTXKmwbtBqzlWD/TUnY58pmg2WUXeso/Ur600g4gddqKac3dJ6P+WT8hjfvkhP22w+ kRaTSv8uELm1luDp9V6GX1AtJV2CXq8JVvzsxTBdbVFKKclMc2NtS0h17ycH591PU9/e inlDLPJQ/9BqYsoTtljgEMkGUPTYnZfKBaLPjZ6zuFAsd75Ame21mr0oibNgf9i60brs bm3g== X-Gm-Message-State: ALKqPwcLBop9qmKWE6+/tOjYEDuAGjy9vUl45SDwRM0fIyC+sVRPuRef giHlX/WP5WY2cMudFlDtLj2nR4hQ474= X-Received: by 2002:a65:4d44:: with SMTP id j4-v6mr3255593pgt.344.1526012608304; Thu, 10 May 2018 21:23:28 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id r76-v6sm4509462pfl.1.2018.05.10.21.23.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 21:23:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 21:23:12 -0700 Message-Id: <20180511042324.5070-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511042324.5070-1-richard.henderson@linaro.org> References: <20180511042324.5070-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 01/13] target-openrisc: Write back result before FPE exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Stafford Horne , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The architecture manual is unclear about this, but the or1ksim does writeback before the exception. This requires splitting the helpers in half, with the exception raised by the second. Acked-by: Stafford Horne Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/openrisc/helper.h | 25 ++-- target/openrisc/fpu_helper.c | 250 +++++++---------------------------- target/openrisc/translate.c | 101 +++++++++----- 3 files changed, 125 insertions(+), 251 deletions(-) -- 2.17.0 diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index 4fd1a6bb8e..e37dabc77a 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -24,17 +24,19 @@ DEF_HELPER_FLAGS_1(ove_ov, TCG_CALL_NO_WG, void, env) DEF_HELPER_FLAGS_1(ove_cyov, TCG_CALL_NO_WG, void, env) /* float */ -DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32) -DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_1(update_fpcsr, TCG_CALL_NO_WG, void, env) -DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32) -DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_RWG, i32, env, i32) + +DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) +DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) #define FOP_CALC(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, i32, env, i32, i32) \ +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, i64, env, i64, i64) FOP_CALC(add) FOP_CALC(sub) FOP_CALC(mul) @@ -43,14 +45,11 @@ FOP_CALC(rem) #undef FOP_CALC #define FOP_CMP(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_RWG, tl, env, i32, i32) \ +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl, env, i64, i64) FOP_CMP(eq) FOP_CMP(lt) FOP_CMP(le) -FOP_CMP(ne) -FOP_CMP(gt) -FOP_CMP(ge) #undef FOP_CMP /* interrupt */ diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 977a1e8e55..265ce13337 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -24,121 +24,70 @@ #include "exception.h" #include "fpu/softfloat.h" -static inline uint32_t ieee_ex_to_openrisc(OpenRISCCPU *cpu, int fexcp) +static int ieee_ex_to_openrisc(int fexcp) { int ret = 0; - if (fexcp) { - if (fexcp & float_flag_invalid) { - cpu->env.fpcsr |= FPCSR_IVF; - ret = 1; - } - if (fexcp & float_flag_overflow) { - cpu->env.fpcsr |= FPCSR_OVF; - ret = 1; - } - if (fexcp & float_flag_underflow) { - cpu->env.fpcsr |= FPCSR_UNF; - ret = 1; - } - if (fexcp & float_flag_divbyzero) { - cpu->env.fpcsr |= FPCSR_DZF; - ret = 1; - } - if (fexcp & float_flag_inexact) { - cpu->env.fpcsr |= FPCSR_IXF; - ret = 1; - } + if (fexcp & float_flag_invalid) { + ret |= FPCSR_IVF; + } + if (fexcp & float_flag_overflow) { + ret |= FPCSR_OVF; + } + if (fexcp & float_flag_underflow) { + ret |= FPCSR_UNF; + } + if (fexcp & float_flag_divbyzero) { + ret |= FPCSR_DZF; + } + if (fexcp & float_flag_inexact) { + ret |= FPCSR_IXF; } - return ret; } -static inline void update_fpcsr(OpenRISCCPU *cpu) +void HELPER(update_fpcsr)(CPUOpenRISCState *env) { - int tmp = ieee_ex_to_openrisc(cpu, - get_float_exception_flags(&cpu->env.fp_status)); + int tmp = get_float_exception_flags(&env->fp_status); - SET_FP_CAUSE(cpu->env.fpcsr, tmp); - if ((GET_FP_ENABLE(cpu->env.fpcsr) & tmp) && - (cpu->env.fpcsr & FPCSR_FPEE)) { - helper_exception(&cpu->env, EXCP_FPE); - } else { - UPDATE_FP_FLAGS(cpu->env.fpcsr, tmp); + if (tmp) { + set_float_exception_flags(0, &env->fp_status); + tmp = ieee_ex_to_openrisc(tmp); + if (tmp) { + env->fpcsr |= tmp; + if (env->fpcsr & FPCSR_FPEE) { + helper_exception(env, EXCP_FPE); + } + } } } uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) { - uint64_t itofd; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - - set_float_exception_flags(0, &cpu->env.fp_status); - itofd = int32_to_float64(val, &cpu->env.fp_status); - update_fpcsr(cpu); - - return itofd; + return int32_to_float64(val, &env->fp_status); } uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) { - uint32_t itofs; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - - set_float_exception_flags(0, &cpu->env.fp_status); - itofs = int32_to_float32(val, &cpu->env.fp_status); - update_fpcsr(cpu); - - return itofs; + return int32_to_float32(val, &env->fp_status); } uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) { - uint64_t ftoid; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - - set_float_exception_flags(0, &cpu->env.fp_status); - ftoid = float32_to_int64(val, &cpu->env.fp_status); - update_fpcsr(cpu); - - return ftoid; + return float32_to_int64(val, &env->fp_status); } uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) { - uint32_t ftois; - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - - set_float_exception_flags(0, &cpu->env.fp_status); - ftois = float32_to_int32(val, &cpu->env.fp_status); - update_fpcsr(cpu); - - return ftois; + return float32_to_int32(val, &env->fp_status); } -#define FLOAT_OP(name, p) void helper_float_##_##p(void) - #define FLOAT_CALC(name) \ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ uint64_t fdt0, uint64_t fdt1) \ -{ \ - uint64_t result; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - result = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return result; \ -} \ - \ +{ return float64_ ## name(fdt0, fdt1, &env->fp_status); } \ uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ uint32_t fdt0, uint32_t fdt1) \ -{ \ - uint32_t result; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - result = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return result; \ -} \ +{ return float32_ ## name(fdt0, fdt1, &env->fp_status); } FLOAT_CALC(add) FLOAT_CALC(sub) @@ -151,132 +100,29 @@ FLOAT_CALC(rem) uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, uint64_t b, uint64_t c) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - uint64_t result; - set_float_exception_flags(0, &cpu->env.fp_status); - /* Note that or1ksim doesn't use merged operation. */ - result = float64_mul(b, c, &cpu->env.fp_status); - result = float64_add(result, a, &cpu->env.fp_status); - update_fpcsr(cpu); - return result; + /* Note that or1ksim doesn't use fused operation. */ + b = float64_mul(b, c, &env->fp_status); + return float64_add(a, b, &env->fp_status); } uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, uint32_t b, uint32_t c) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - uint32_t result; - set_float_exception_flags(0, &cpu->env.fp_status); - /* Note that or1ksim doesn't use merged operation. */ - result = float32_mul(b, c, &cpu->env.fp_status); - result = float32_add(result, a, &cpu->env.fp_status); - update_fpcsr(cpu); - return result; + /* Note that or1ksim doesn't use fused operation. */ + b = float32_mul(b, c, &env->fp_status); + return float32_add(a, b, &env->fp_status); } -#define FLOAT_CMP(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1)\ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} +#define FLOAT_CMP(name, impl) \ +target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \ + uint64_t fdt0, uint64_t fdt1) \ +{ return float64_ ## impl(fdt0, fdt1, &env->fp_status); } \ +target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \ + uint32_t fdt0, uint32_t fdt1) \ +{ return float32_ ## impl(fdt0, fdt1, &env->fp_status); } -FLOAT_CMP(le) -FLOAT_CMP(eq) -FLOAT_CMP(lt) +FLOAT_CMP(le, le) +FLOAT_CMP(lt, lt) +FLOAT_CMP(eq, eq_quiet) #undef FLOAT_CMP - - -#define FLOAT_CMPNE(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float64_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float32_eq_quiet(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} - -FLOAT_CMPNE(ne) -#undef FLOAT_CMPNE - -#define FLOAT_CMPGT(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float64_le(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float32_le(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} -FLOAT_CMPGT(gt) -#undef FLOAT_CMPGT - -#define FLOAT_CMPGE(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float64_lt(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ -{ \ - int res; \ - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ - set_float_exception_flags(0, &cpu->env.fp_status); \ - res = !float32_lt(fdt0, fdt1, &cpu->env.fp_status); \ - update_fpcsr(cpu); \ - return res; \ -} - -FLOAT_CMPGE(ge) -#undef FLOAT_CMPGE diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 2747b24cf0..6876317971 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1294,180 +1294,209 @@ static void dec_float(DisasContext *dc, uint32_t insn) rd = extract32(insn, 21, 5); switch (op0) { - case 0x00: /* lf.add.s */ + case 0x00: /* lf.add.s */ LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x01: /* lf.sub.s */ + case 0x01: /* lf.sub.s */ LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; case 0x02: /* lf.mul.s */ LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x03: /* lf.div.s */ + case 0x03: /* lf.div.s */ LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x04: /* lf.itof.s */ + case 0x04: /* lf.itof.s */ LOG_DIS("lf.itof r%d, r%d\n", rd, ra); check_r0_write(rd); gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x05: /* lf.ftoi.s */ + case 0x05: /* lf.ftoi.s */ LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); check_r0_write(rd); gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x06: /* lf.rem.s */ + case 0x06: /* lf.rem.s */ LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x07: /* lf.madd.s */ + case 0x07: /* lf.madd.s */ LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); check_r0_write(rd); gen_helper_float_madd_s(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x08: /* lf.sfeq.s */ + case 0x08: /* lf.sfeq.s */ LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb); gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x09: /* lf.sfne.s */ + case 0x09: /* lf.sfne.s */ LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb); - gen_helper_float_ne_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); + gen_helper_update_fpcsr(cpu_env); break; - case 0x0a: /* lf.sfgt.s */ + case 0x0a: /* lf.sfgt.s */ LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb); - gen_helper_float_gt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x0b: /* lf.sfge.s */ + case 0x0b: /* lf.sfge.s */ LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb); - gen_helper_float_ge_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x0c: /* lf.sflt.s */ + case 0x0c: /* lf.sflt.s */ LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb); gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x0d: /* lf.sfle.s */ + case 0x0d: /* lf.sfle.s */ LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb); gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - case 0x10: lf.add.d +#ifdef TARGET_OPENRISC64 + case 0x10: /* lf.add.d */ LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x11: lf.sub.d + case 0x11: /* lf.sub.d */ LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x12: lf.mul.d + case 0x12: /* lf.mul.d */ LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x13: lf.div.d + case 0x13: /* lf.div.d */ LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x14: lf.itof.d + case 0x14: /* lf.itof.d */ LOG_DIS("lf.itof r%d, r%d\n", rd, ra); check_of64s(dc); check_r0_write(rd); gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x15: lf.ftoi.d + case 0x15: /* lf.ftoi.d */ LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); check_of64s(dc); check_r0_write(rd); gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x16: lf.rem.d + case 0x16: /* lf.rem.d */ LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x17: lf.madd.d + case 0x17: /* lf.madd.d */ LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); check_of64s(dc); check_r0_write(rd); gen_helper_float_madd_d(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x18: lf.sfeq.d + case 0x18: /* lf.sfeq.d */ LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb); check_of64s(dc); gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x1a: lf.sfgt.d + case 0x1a: /* lf.sfgt.d */ LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_gt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x1b: lf.sfge.d + case 0x1b: /* lf.sfge.d */ LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_ge_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x19: lf.sfne.d + case 0x19: /* lf.sfne.d */ LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb); check_of64s(dc); - gen_helper_float_ne_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); + gen_helper_update_fpcsr(cpu_env); break; - case 0x1c: lf.sflt.d + case 0x1c: /* lf.sflt.d */ LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb); check_of64s(dc); gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; - case 0x1d: lf.sfle.d + case 0x1d: /* lf.sfle.d */ LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb); check_of64s(dc); gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); + gen_helper_update_fpcsr(cpu_env); break; -#endif*/ +#endif default: gen_illegal_exception(dc);