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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id r76-v6sm4509462pfl.1.2018.05.10.21.23.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 21:23:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 21:23:24 -0700 Message-Id: <20180511042324.5070-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511042324.5070-1-richard.henderson@linaro.org> References: <20180511042324.5070-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PULL 13/13] target/openrisc: Merge disas_openrisc_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Acked-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) -- 2.17.0 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 66e493220e..3866106bf6 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1373,14 +1373,6 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn) return true; } -static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) -{ - uint32_t insn = cpu_ldl_code(&cpu->env, dc->pc); - if (!decode(dc, insn)) { - gen_illegal_exception(dc); - } -} - void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) { CPUOpenRISCState *env = cs->env_ptr; @@ -1388,6 +1380,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) struct DisasContext ctx, *dc = &ctx; uint32_t pc_start; uint32_t next_page_start; + uint32_t insn; int num_insns; int max_insns; @@ -1449,7 +1442,11 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } - disas_openrisc_insn(dc, cpu); + + insn = cpu_ldl_code(&cpu->env, dc->pc); + if (!decode(dc, insn)) { + gen_illegal_exception(dc); + } dc->pc = dc->pc + 4; /* delay slot */