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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id e18-v6sm3495636pfi.100.2018.05.10.20.52.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 20:52:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 20:52:36 -0700 Message-Id: <20180511035240.4016-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511035240.4016-1-richard.henderson@linaro.org> References: <20180511035240.4016-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 5/9] target/riscv: Honor CPU_DUMP_FPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael Clark diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e5a56d4e3..4612f324c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -199,6 +199,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int i; cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); + if (flags & CPU_DUMP_FPU) { + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "fcsr ", + cpu_riscv_get_fcsr(env)); + } #ifndef CONFIG_USER_ONLY cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); @@ -219,11 +223,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, "\n"); } } - for (i = 0; i < 32; i++) { - cpu_fprintf(f, " %s %016" PRIx64, - riscv_fpr_regnames[i], env->fpr[i]); - if ((i & 3) == 3) { - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < 32; i++) { + cpu_fprintf(f, " %s %016" PRIx64, + riscv_fpr_regnames[i], env->fpr[i]); + if ((i & 3) == 3) { + cpu_fprintf(f, "\n"); + } } } }